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spi读0x100将会暂存后续寄存器防止进位

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Ruige Lee
2025-08-26 11:35:47 +08:00
parent 249a94a64b
commit 6b118fa498
1 changed files with 7 additions and 7 deletions
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14
src/main/scala/backBoard/shin/Interface.scala
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@@ -379,13 +379,13 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
Seq( Seq(
//本地时钟 //本地时钟
(addr === "h100".U ) -> cReg.timeStamp(7,0), (addr === "h100".U ) -> cReg.timeStamp(7,0),
(addr === "h101".U ) -> cReg.timeStamp(15,8), (addr === "h101".U ) -> RegEnable(cReg.timeStamp(15,8), isEnR & addrr === "h100".U),
(addr === "h102".U ) -> cReg.timeStamp(23,16), (addr === "h102".U ) -> RegEnable(cReg.timeStamp(23,16), isEnR & addrr === "h100".U),
(addr === "h103".U ) -> cReg.timeStamp(31,24), (addr === "h103".U ) -> RegEnable(cReg.timeStamp(31,24), isEnR & addrr === "h100".U),
(addr === "h104".U ) -> cReg.timeStamp(39,32), (addr === "h104".U ) -> RegEnable(cReg.timeStamp(39,32), isEnR & addrr === "h100".U),
(addr === "h105".U ) -> cReg.timeStamp(47,40), (addr === "h105".U ) -> RegEnable(cReg.timeStamp(47,40), isEnR & addrr === "h100".U),
(addr === "h106".U ) -> cReg.timeStamp(55,48), (addr === "h106".U ) -> RegEnable(cReg.timeStamp(55,48), isEnR & addrr === "h100".U),
(addr === "h107".U ) -> cReg.timeStamp(63,56), (addr === "h107".U ) -> RegEnable(cReg.timeStamp(63,56), isEnR & addrr === "h100".U),
//参考主站时钟 //参考主站时钟
(addr === "h108".U & isSlvMode) -> sReg.deltaFinal(7,0), (addr === "h108".U & isSlvMode) -> sReg.deltaFinal(7,0),