From 69ccc32603b01a7a8da8dfb6b63bd2195f1a7c5a Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Fri, 20 Oct 2023 20:56:44 +0800
Subject: [PATCH] =?UTF-8?q?=E5=9C=A832=E6=95=B0=E6=8D=AE=E9=80=9A=E9=81=93?=
 =?UTF-8?q?=E4=B8=8B=E4=BC=A0=E8=BE=93=E6=AD=A3=E7=A1=AE?=
MIME-Version: 1.0
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---
 src/main/scala/Switch/SwitchMux.scala         |  4 +-
 src/main/scala/Switch/TxBuff.scala            | 56 +++++++++++++++----
 src/main/scala/Switch/mac/MacTileLinkTx.scala |  6 +-
 src/main/scala/Switch/mac/MacTilelink.scala   |  2 +-
 4 files changed, 53 insertions(+), 15 deletions(-)

diff --git a/src/main/scala/Switch/SwitchMux.scala b/src/main/scala/Switch/SwitchMux.scala
index 93e9d45..b924333 100644
--- a/src/main/scala/Switch/SwitchMux.scala
+++ b/src/main/scala/Switch/SwitchMux.scala
@@ -53,7 +53,7 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
 
 
     def ptr = "h80002000".U
-    def txLength       = 8.U
+    def txLength       = 64.U
     def PerPacketCrcEn = true.B
     def PerPacketPad   = true.B
 
@@ -93,7 +93,7 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
 
   val dmaAddress = Reg( UInt(32.W) )
 
-  when( stateCur === stateIdle && stateNxt =/= stateIdle ){
+  when( stateCur === stateIdle ){
     dmaAddress := ptr
   } .elsewhen( io.dmaMst.A.fire ){
     dmaAddress := dmaAddress + 4.U
diff --git a/src/main/scala/Switch/TxBuff.scala b/src/main/scala/Switch/TxBuff.scala
index 387a2e7..e66cef1 100644
--- a/src/main/scala/Switch/TxBuff.scala
+++ b/src/main/scala/Switch/TxBuff.scala
@@ -35,21 +35,57 @@ class TxBuffIO extends Bundle{
 }
 
 
-class TxBuff extends Module{
+abstract class TxBuffBase extends Module{
   val io: TxBuffIO = IO(new TxBuffIO)
 
-  io.enq.data.ready := true.B
-  io.enq.req.ready := true.B
 
-  io.enq.resp.valid := false.B
-  io.enq.resp.bits := DontCare
 
-  io.deq.data.valid := false.B
-  io.deq.data.bits  := 0.U
+  val buff = Module(new Queue( UInt(32.W), 2048/4 ))
+  val reqInfo = Reg(new Transmit_Req_Bundle)
+  val respInfo = Reg(new Transmit_Resp_Bundle)
+  val enqCnt = Reg(UInt(16.W))
+  val deqReqValid = RegInit(false.B)
+
 
-  io.deq.req.valid := false.B
-  io.deq.req.bits  := DontCare
 
-  io.deq.resp.ready := true.B
   
 }
+
+
+trait TxBuffEnq{ this: TxBuffBase =>
+    io.enq.data <> buff.io.enq
+
+
+    when( io.enq.req.fire ){
+      enqCnt := 0.U
+      reqInfo := io.enq.req.bits
+    } .elsewhen( io.enq.data.fire ){
+      enqCnt := enqCnt + 4.U
+      // when( enqCnt + 4.U >= reqInfo.txLength ){
+      // }
+    }
+
+
+  io.enq.req.ready := ~buff.io.deq.valid
+
+
+  when( io.deq.req.fire ){
+    deqReqValid := false.B
+  } .elsewhen( io.enq.data.fire && enqCnt === 32.U ) {
+    deqReqValid := true.B
+  }
+
+}
+
+trait TxBuffDeq{ this: TxBuffBase =>
+  io.deq.resp <> io.enq.resp
+
+  io.deq.req.valid := deqReqValid
+  io.deq.req.bits  := reqInfo
+
+  io.deq.data <> buff.io.deq
+
+}
+
+
+class TxBuff extends TxBuffBase with TxBuffEnq with TxBuffDeq
diff --git a/src/main/scala/Switch/mac/MacTileLinkTx.scala b/src/main/scala/Switch/mac/MacTileLinkTx.scala
index 41b63ce..8620ce5 100644
--- a/src/main/scala/Switch/mac/MacTileLinkTx.scala
+++ b/src/main/scala/Switch/mac/MacTileLinkTx.scala
@@ -112,8 +112,10 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
     TxByteCnt := TxByteCnt + 1.U
   }
 
-  when(io.TxStartFrm_sync & ~TxStartFrm | io.TxUsedData & Flop & TxByteCnt === 3.U &
-    ~LastWord | TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U ){
+  when(
+    io.TxStartFrm_sync & ~TxStartFrm |
+    io.TxUsedData & Flop & TxByteCnt === 3.U & ~LastWord |
+    TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U ){
     ReadTxDataFromFifo_tck := true.B
   } .elsewhen(io.ReadTxDataFromFifo_syncb & ~RegNext(io.ReadTxDataFromFifo_syncb, false.B)){
     ReadTxDataFromFifo_tck := false.B
diff --git a/src/main/scala/Switch/mac/MacTilelink.scala b/src/main/scala/Switch/mac/MacTilelink.scala
index a2a1b5b..9048f4a 100644
--- a/src/main/scala/Switch/mac/MacTilelink.scala
+++ b/src/main/scala/Switch/mac/MacTilelink.scala
@@ -144,7 +144,7 @@ abstract class MacTileLinkBase() extends Module{
   }
 
 
-  when((TxLength === 0.U) & io.TxUsedData){
+  when(((TxLength - 4.U) === 0.U) & io.TxUsedData){
     TxEndFrm_wb := true.B
   } .elsewhen(txRetryPulse | txDonePulse | txAbortPulse){
     TxEndFrm_wb := false.B