crc cleanup

src/main/scala/Switch/MacRegisters.scala

@@ -26,9 +26,6 @@ class Mac_Config_Bundle extends Bundle{
   val TxClk               = Input(Bool())
   val RxClk               = Input(Bool())
 
-  val r_HugEn     = Output(Bool())
-  val r_CrcEn     = Output(Bool())
-  val r_DlyCrcEn  = Output(Bool())
   val r_FullD     = Output(Bool())
   val r_ExDfrEn   = Output(Bool())
   val r_LoopBck   = Output(Bool())
@@ -92,9 +89,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
     val (int, _) = outer.int_node.out(0)
 
 
-    val HugEn     = RegInit(false.B)
-    val CrcEn     = RegInit(true.B)
-    val DlyCrcEn  = RegInit(false.B)
 
     val FullD     = RegInit(false.B)
     val ExDfrEn   = RegInit(false.B)
@@ -175,8 +169,8 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
           RegField(1, ExDfrEn, RegFieldDesc( "ExDfrEn", "ExDfrEn", reset = Some(0) ) ),
           RegField(1, FullD  , RegFieldDesc( "FullD", "FullD", reset = Some(0) ) ),
           RegField.r(1, 0.U),
-          RegField(1, DlyCrcEn, RegFieldDesc( "DlyCrcEn", "DlyCrcEn", reset=Some(0)) ),
+          RegField.r(1, 0.U, RegFieldDesc( "DlyCrcEn", "DlyCrcEn", reset=Some(0)) ),
-          RegField(1, CrcEn   , RegFieldDesc( "CrcEn", "CrcEn",       reset=Some(1)) ),
+          RegField.r(1, 0.U, RegFieldDesc( "CrcEn", "CrcEn",       reset=Some(1)) ),
           RegField.r(1, 1.U   , RegFieldDesc( "HugEn", "HugEn",       reset=Some(0)) ),
           RegField.r(1, 1.U   , RegFieldDesc( "Pad", "Pad",           reset=Some(1)) ),
           RegField.r(1, 1.U,    RegFieldDesc( "RecSmall", "RecSmall", reset=Some(0)) )
@@ -325,9 +319,6 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
 
 
 
-    io.r_HugEn     := HugEn
-    io.r_CrcEn     := CrcEn
-    io.r_DlyCrcEn  := DlyCrcEn
     io.r_FullD     := FullD
     io.r_ExDfrEn   := ExDfrEn
     io.r_LoopBck   := LoopBck

src/main/scala/Switch/mac/MAC.scala

@@ -140,7 +140,6 @@ val MRxDV_Lb                   = Wire(Bool())
 val MRxErr_Lb                  = Wire(Bool())
 val MRxD_Lb                    = Wire(UInt(4.W))
 val Transmitting               = Wire(Bool())
-val r_DlyCrcEn                 = Wire(Bool())
 val DribbleNibble              = Wire(Bool())
 val LoadRxStatus               = Wire(Bool())
 val r_HASH0                    = Wire(UInt(32.W))
@@ -156,7 +155,6 @@ val TxE_IRQ                    = Wire(Bool())
 val RxB_IRQ                    = Wire(Bool())
 val RxE_IRQ                    = Wire(Bool())
 val Busy_IRQ                   = Wire(Bool())
-val r_CrcEn                    = Wire(Bool())
 val r_FullD                    = Wire(Bool())
 val r_NoPre                    = Wire(Bool())
 val StartTxDone                = Wire(Bool())
@@ -175,7 +173,6 @@ dontTouch(MRxDV_Lb                   )
 dontTouch(MRxErr_Lb                  )
 dontTouch(MRxD_Lb                    )
 dontTouch(Transmitting               )
-dontTouch(r_DlyCrcEn                 )
 dontTouch(DribbleNibble              )
 dontTouch(LoadRxStatus               )
 dontTouch(r_HASH0                    )
@@ -191,7 +188,6 @@ dontTouch(TxE_IRQ                    )
 dontTouch(RxB_IRQ                    )
 dontTouch(RxE_IRQ                    )
 dontTouch(Busy_IRQ                   )
-dontTouch(r_CrcEn                    )
 dontTouch(r_FullD                    )
 dontTouch(r_NoPre                    )
 dontTouch(StartTxDone                )
@@ -224,8 +220,6 @@ io.cfg.StartTxDone         := StartTxDone
 io.cfg.TxClk               := io.mii.mtx_clk_pad_i
 io.cfg.RxClk               := io.mii.mrx_clk_pad_i
 
-r_CrcEn     := io.cfg.r_CrcEn
-r_DlyCrcEn  := io.cfg.r_DlyCrcEn
 r_FullD     := io.cfg.r_FullD
 r_ExDfrEn   := io.cfg.r_ExDfrEn
 r_LoopBck   := io.cfg.r_LoopBck
@@ -333,9 +327,8 @@ txethmac.io.TxEndFrm        := TxEndFrm
 txethmac.io.TxData          := TxData
 txethmac.io.CarrierSense    := TxCarrierSense
 txethmac.io.Collision       := Collision
-txethmac.io.CrcEn           := r_CrcEn | PerPacketCrcEn
+txethmac.io.CrcEn           := PerPacketCrcEn
 txethmac.io.FullD           := r_FullD
-txethmac.io.DlyCrcEn        := r_DlyCrcEn
 txethmac.io.IPGT            := r_IPGT
 txethmac.io.IPGR1           := r_IPGR1
 txethmac.io.IPGR2           := r_IPGR2
@@ -387,7 +380,6 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   rxethmac.io.MRxDV               := MRxDV_Lb
   rxethmac.io.MRxD                := MRxD_Lb
   rxethmac.io.Transmitting        := Transmitting
-  rxethmac.io.DlyCrcEn            := r_DlyCrcEn
   rxethmac.io.r_IFG               := r_IFG
   rxethmac.io.r_HASH0             := r_HASH0
   rxethmac.io.r_HASH1             := r_HASH1

src/main/scala/Switch/mac/MacRx.scala

@@ -10,7 +10,6 @@ class MacRxIO extends Bundle{
   val MRxDV               = Input(Bool())
   val MRxD                = Input(UInt(4.W))
   val Transmitting        = Input(Bool())
-  val DlyCrcEn            = Input(Bool())
   val r_IFG               = Input(Bool())
   val r_HASH0             = Input(UInt(32.W)) //  lower 4 bytes Hash Table
   val r_HASH1             = Input(UInt(32.W)) //  upper 4 bytes Hash Table
@@ -51,7 +50,6 @@ abstract class MacRxBase extends Module with RequireAsyncReset{
 
   val ByteCntSmall7 = Wire(Bool())
 
-  val DlyCrcCnt  = RegInit(0.U(4.W))
 
   val StateData0    = RegInit(false.B)
   val StateData1    = RegInit(false.B)
@@ -137,19 +135,14 @@ trait MacRxCounter { this: MacRxBase =>
   val IncrementByteCounter =
     ~ResetByteCounter & io.MRxDV & (
       io.StatePreamble | io.StateSFD | io.StateIdle & ~io.Transmitting |
-      (io.StateData.extract(1) & ~ByteCntMax & ~(io.DlyCrcEn & DlyCrcCnt.orR))
+      (io.StateData.extract(1) & ~ByteCntMax)
     )
 
   val ByteCntDelayed = ByteCnt + 4.U
-  io.ByteCnt := Mux(io.DlyCrcEn, ByteCntDelayed, ByteCnt)
+  io.ByteCnt := ByteCnt
+
+
 
-  when( DlyCrcCnt === 9.U ){
-    DlyCrcCnt := 0.U
-  } .elsewhen(io.DlyCrcEn & io.StateSFD){
-    DlyCrcCnt := 1.U
-  } .elsewhen(io.DlyCrcEn & (DlyCrcCnt.orR)){
-    DlyCrcCnt :=  DlyCrcCnt + 1.U
-  }
 
   when( ResetByteCounter ){
     ByteCnt := 0.U
@@ -221,7 +214,7 @@ trait MacRxCRC { this: MacRxBase =>
 
   val Data_Crc   = Cat(io.MRxD.extract(0),io.MRxD.extract(1),io.MRxD.extract(2),io.MRxD.extract(3))
   val Enable_Crc = io.MRxDV & (io.StateData.orR)
-  val Initialize_Crc = io.StateSFD | (io.DlyCrcEn & DlyCrcCnt > 0.U & DlyCrcCnt < 9.U)
+  val Initialize_Crc = io.StateSFD
 
   when( Initialize_Crc ){
     Crc := "hFFFFFFFF".U
@@ -271,7 +264,7 @@ class MacRx extends MacRxBase with MacRxFSM with MacRxCounter with MacRxFAddrChe
 
 
 
-  val GenerateRxValid = StateData0 & (~ByteCntEq0 | DlyCrcCnt >= 3.U);
+  val GenerateRxValid = StateData0 & ~ByteCntEq0;
   val DelayData   = RegNext(StateData0, false.B)
   val LatchedByte = RegInit(0.U(8.W))
   when(true.B) {
@@ -291,7 +284,7 @@ class MacRx extends MacRxBase with MacRxFSM with MacRxCounter with MacRxFAddrChe
   io.RxValid := ShiftRegister(GenerateRxValid, 2, false.B, true.B)
 
 
-  val GenerateRxStartFrm = StateData0 & ( (ByteCntEq1 & ~io.DlyCrcEn) | ((DlyCrcCnt === 3.U) & io.DlyCrcEn) )
+  val GenerateRxStartFrm = StateData0 & ByteCntEq1
 
   io.RxStartFrm := ShiftRegister(GenerateRxStartFrm, 2, false.B, true.B)