加入常数定义

2024-07-16 15:36:40 +08:00
parent 71a489a1d0
commit 693621f1a0
8 changed files with 360 additions and 12 deletions
--- a/src/main/verilog/spi_top.v
+++ b/src/main/verilog/spi_top.v
@@ -149,7 +149,10 @@ Gowin_PLLO Gowin_PLLO(
  .clkin(clock)
 );

-
+wire lvds_down_din;
+wire lvds_down_dout;
+wire lvds_up_din;
+wire lvds_up_dout;

 TLVDS_OBUF lvds_downstream_out(
  .O(lvds_down_dout_p),
@@ -291,6 +294,8 @@ SpiSlv i_spiSlv(
  .io_isLast(isLast_temp1),
  .io_DCIn(DCIn),

+  .param_pl(`PL),
+  .param_npl(`NPL),
  .param_vendorID(`VENDORID),
  .param_moduleID(`MODULEID),
  .param_hwVersion(`HWVERSION),