加入常数定义

src/main/verilog/do16_top.v

@@ -147,7 +147,10 @@ Gowin_PLLO Gowin_PLLO(
   .clkin(clock)
 );
 
-
+wire lvds_down_din;
+wire lvds_down_dout;
+wire lvds_up_din;
+wire lvds_up_dout;
 
 TLVDS_OBUF lvds_downstream_out(
   .O(lvds_down_dout_p),
@@ -289,11 +292,13 @@ DOut16 i_dout16(
   .io_isLast(isLast_temp1),
   .io_DCIn(DCIn),
 
+  .param_pl(`PL),
+  .param_npl(`NPL),
   .param_vendorID(`VENDORID),
   .param_moduleID(`MODULEID),
   .param_hwVersion(`HWVERSION),
   .param_swVersion(`SWVERSION),
-  // .param_batchID(`BATCHID),
+
   .param_serial(`SERIAL),
   .LED_PR(LED_PR),
   .LED_ERR(LED_ERR),