加入常数定义

src/main/verilog/di16_top.v

@@ -140,7 +140,10 @@ Gowin_PLLO Gowin_PLLO(
   .clkin(clock)
 );
 
-
+wire lvds_down_din;
+wire lvds_down_dout;
+wire lvds_up_din;
+wire lvds_up_dout;
 
 TLVDS_OBUF lvds_downstream_out(
   .O(lvds_down_dout_p),
@@ -228,6 +231,8 @@ wire [7:0] upstream_tx_data_in;
 wire downstream_rx_cdr_err;
 wire upstream_rx_cdr_err;
 
+
+
 lvds_bus_slave_top i_lvds_bus_slave(
   .rst_n(resetn && resetn1),
   .reset_calib(reset_calib),
@@ -281,6 +286,8 @@ DIn16 i_din16(
   .io_isLast(isLast_temp1),
   .io_DCIn(DCIn),
 
+  .param_pl(`PL),
+  .param_npl(`NPL),
   .param_vendorID(`VENDORID),
   .param_moduleID(`MODULEID),
   .param_hwVersion(`HWVERSION),