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加入常数定义

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This commit is contained in:
RuigeLee
2024-07-16 15:36:40 +08:00
parent 71a489a1d0
commit 693621f1a0
8 changed files with 360 additions and 12 deletions
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2
src/main/verilog/defineParam.v
View File

@@ -1,3 +1,5 @@
`define PL 16'h0002
`define NPL 16'h0004
`define VENDORID 16'h1122
`define MODULEID 16'h3344
`define HWVERSION 16'h5566

9
src/main/verilog/di16_top.v
View File

@@ -140,7 +140,10 @@ Gowin_PLLO Gowin_PLLO(
.clkin(clock)
);
wire lvds_down_din;
wire lvds_down_dout;
wire lvds_up_din;
wire lvds_up_dout;
TLVDS_OBUF lvds_downstream_out(
.O(lvds_down_dout_p),
@@ -228,6 +231,8 @@ wire [7:0] upstream_tx_data_in;
wire downstream_rx_cdr_err;
wire upstream_rx_cdr_err;
lvds_bus_slave_top i_lvds_bus_slave(
.rst_n(resetn && resetn1),
.reset_calib(reset_calib),
@@ -281,6 +286,8 @@ DIn16 i_din16(
.io_isLast(isLast_temp1),
.io_DCIn(DCIn),
.param_pl(`PL),
.param_npl(`NPL),
.param_vendorID(`VENDORID),
.param_moduleID(`MODULEID),
.param_hwVersion(`HWVERSION),

9
src/main/verilog/do16_top.v
View File

@@ -147,7 +147,10 @@ Gowin_PLLO Gowin_PLLO(
.clkin(clock)
);
wire lvds_down_din;
wire lvds_down_dout;
wire lvds_up_din;
wire lvds_up_dout;
TLVDS_OBUF lvds_downstream_out(
.O(lvds_down_dout_p),
@@ -289,11 +292,13 @@ DOut16 i_dout16(
.io_isLast(isLast_temp1),
.io_DCIn(DCIn),
.param_pl(`PL),
.param_npl(`NPL),
.param_vendorID(`VENDORID),
.param_moduleID(`MODULEID),
.param_hwVersion(`HWVERSION),
.param_swVersion(`SWVERSION),
// .param_batchID(`BATCHID),
.param_serial(`SERIAL),
.LED_PR(LED_PR),
.LED_ERR(LED_ERR),

321
src/main/verilog/do16inv_top.v Normal file
View File

@@ -0,0 +1,321 @@
module do16_top(
input clock,
input lvds_up_din_p,
input lvds_up_din_n,
output lvds_up_dout_p,
output lvds_up_dout_n,
input lvds_down_din_p,
input lvds_down_din_n,
output lvds_down_dout_p,
output lvds_down_dout_n,
output isOnline,
input isLast,
input DCIn,
output LED_PR,
output LED_ERR,
output [15:0] out,
input flt_0,
input flt_1,
input v24Det
);
wire clk_400m;
wire clk_400m_a;
wire clk_100m_a;
wire clk_50m_a;
wire clk_10m_a;
wire lock_o;
wire reset_stop;
wire reset_calib;
reg rst_n;
reg rstn_d;
wire resetn;
reg resetn1=1'b1;
wire timeout_rst;
reg timeout_rst_d1;
reg timeout_rst_d2;
reg timeout_rst_d3;
reg timeout_rst_d4;
reg timeout_rst_d5;
reg timeout_rst_d6;
reg timeout_rst_d7;
reg timeout_rst_d8;
reg [3:0] resetCnt = 4'd0;
always @( posedge clock ) begin
if( resetCnt != 4'd15 ) begin
resetCnt <= resetCnt + 4'd1;
end
end
assign resetn = resetCnt == 4'd15;
always@(posedge clock or negedge resetn) begin
if(!resetn) begin
timeout_rst_d1 <= 0;
timeout_rst_d2 <= 0;
timeout_rst_d3 <= 0;
timeout_rst_d4 <= 0;
timeout_rst_d5 <= 0;
timeout_rst_d6 <= 0;
timeout_rst_d7 <= 0;
timeout_rst_d8 <= 0;
end
else begin
timeout_rst_d1 <= timeout_rst;
timeout_rst_d2 <= timeout_rst_d1;
timeout_rst_d3 <= timeout_rst_d2;
timeout_rst_d4 <= timeout_rst_d3;
timeout_rst_d5 <= timeout_rst_d4;
timeout_rst_d6 <= timeout_rst_d5;
timeout_rst_d7 <= timeout_rst_d6;
timeout_rst_d8 <= timeout_rst_d7;
end
end
always @(posedge clock or negedge resetn) begin
if(!resetn) begin
resetn1 <= 1'b1;
end else if((timeout_rst_d3 == 1'b0) && (timeout_rst_d2 == 1'b1)) begin
resetn1 <= 1'b0;
end else if((timeout_rst_d4 == 1'b0) && (timeout_rst_d3 == 1'b1)) begin
resetn1 <= 1'b0;
end else if((timeout_rst_d5 == 1'b0) && (timeout_rst_d4 == 1'b1)) begin
resetn1 <= 1'b0;
end else if((timeout_rst_d6 == 1'b0) && (timeout_rst_d5 == 1'b1)) begin
resetn1 <= 1'b0;
end else if((timeout_rst_d7 == 1'b0) && (timeout_rst_d6 == 1'b1)) begin
resetn1 <= 1'b0;
end else if((timeout_rst_d8 == 1'b0) && (timeout_rst_d7 == 1'b1)) begin
resetn1 <= 1'b0;
end else begin
resetn1 <= 1'b1;
end
end
reg [5:0] delay_io_last=6'b111111;
reg [15:0] counter0=0;
reg clk_en0;
wire isLast_temp;
wire isLast_temp1;
always @(posedge clk_10m_a or negedge resetn) begin
if(!resetn) begin
counter0 <= 16'd0;
clk_en0 <= 1'b0;
end else if(counter0 == 16'd9999) begin
counter0 <= 16'd0;
clk_en0 <= 1'b1;
end else begin
counter0 <= counter0 + 1;
clk_en0 <= 1'b0;
end
end
always @(posedge clk_10m_a or negedge resetn) begin
if(!resetn) begin
delay_io_last <= 6'b111111;
end else if(clk_en0 == 1'b1) begin
delay_io_last[5:1] <= delay_io_last[4:0];
delay_io_last[0] <= isLast;
end
end
assign isLast_temp = &{!delay_io_last[5],!delay_io_last[4],!delay_io_last[3],!delay_io_last[2],!delay_io_last[1]};
assign isLast_temp1 = ~isLast_temp;
Gowin_PLLO Gowin_PLLO(
.lock(lock_o),
.clkouta(clk_400m),
.clkin(clock)
);
wire lvds_down_din;
wire lvds_down_dout;
wire lvds_up_din;
wire lvds_up_dout;
TLVDS_OBUF lvds_downstream_out(
.O(lvds_down_dout_p),
.OB(lvds_down_dout_n),
.I(lvds_down_dout)
);
TLVDS_IBUF lvds_downstream_in(
.O(lvds_down_din),
.I(lvds_down_din_p),
.IB(lvds_down_din_n)
);
TLVDS_OBUF lvds_upstream_out(
.O(lvds_up_dout_p),
.OB(lvds_up_dout_n),
.I(lvds_up_dout)
);
TLVDS_IBUF lvds_upstream_in(
.O(lvds_up_din),
.I(lvds_up_din_p),
.IB(lvds_up_din_n)
);
DHCEN dhcen_inst2 (
.CLKIN(clk_400m),
.CE(reset_stop),
.CLKOUT(clk_400m_a)
);
//reset sync module, all the IDES/OSER and related CLKDIV MUST be reset by this module
oser_rst u_oser_rst(
.clk_in(clock), // or any other speed comparble with fabric, DO NOT use HCLK as fabric cannot work at so high speed.
.rst_n(resetn && resetn1),
.pll_lock(lock_o), // trigged by PLL Lock
.reset_stop(reset_stop), // for DHCEN CE
.reset_calib(reset_calib), // for IDES and CLKDIV reset
.set_calib(),
.ready()
);
defparam Inst4_CLKDIVC.DIV_MODE="4";
defparam Inst4_CLKDIVC.GSREN="false";
CLKDIV Inst4_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_400m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_100m_a)
);
defparam Inst2_CLKDIVC.DIV_MODE="2";
defparam Inst2_CLKDIVC.GSREN="false";
CLKDIV Inst2_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_100m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_50m_a)
);
defparam Inst5_CLKDIVC.DIV_MODE="5";
defparam Inst5_CLKDIVC.GSREN="false";
CLKDIV Inst5_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_50m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_10m_a)
);
wire [7:0] downstream_rx_data_out;
wire downstream_rx_data_valid;
wire downstream_rx_crc_valid;
wire downstream_rx_crc_err;
wire upstream_tx_data_ready;
wire [7:0] upstream_tx_data_in;
wire downstream_rx_cdr_err;
wire upstream_rx_cdr_err;
lvds_bus_slave_top i_lvds_bus_slave(
.rst_n(resetn && resetn1),
.reset_calib(reset_calib),
.oser_pclk(clk_10m_a),
.oser_fclk(clk_50m_a),
.ides_pclk(clk_100m_a),
.ides_fclk(clk_400m_a),
.timeout_rst(timeout_rst), //add 240523
.lvds_down_din(lvds_down_din),
.lvds_down_dout(lvds_down_dout),
.lvds_up_din(lvds_up_din),
.lvds_up_dout(lvds_up_dout),
.downstream_rx_data_valid(downstream_rx_data_valid),
.downstream_rx_unicast_pkg_valid(),
.downstream_rx_data_out(downstream_rx_data_out),
.downstream_rx_crc_valid(downstream_rx_crc_valid),
.downstream_rx_crc_err(downstream_rx_crc_err),
.downstream_rx_crc_err_counter(),
.downstream_rx_cdr_err(downstream_rx_cdr_err),
.downstream_sync(),
.upstream_tx_data_ready(upstream_tx_data_ready),
.upstream_tx_unicast_pkg_ready(),
.upstream_tx_data_in(upstream_tx_data_in),
.upstream_rx_crc_valid(),
.upstream_rx_crc_err(),
.upstream_rx_crc_err_counter(),
.upstream_rx_cdr_err(upstream_rx_cdr_err),
.local_slave_id(),
.test_downstream_rx_10b_data(),
.test_downstream_rx_8b_data(),
.test_downstream_rx_state_machine(),
.test_downstream_tx_en(),
.test_downstream_tx_8b_data(),
.test_downstream_tx_10b_data(),
.test_upstream_rx_10b_data(),
.test_upstream_rx_8b_data(),
.test_upstream_rx_state_machine(),
.test_upstream_tx_en(),
.test_upstream_tx_8b_data(),
.test_upstream_tx_10b_data()
);
wire [15:0] outInv;
assign out = ~outInv;
DOut16 i_dout16(
.reset(~resetn),
.clock(clk_10m_a),
.io_isOnline(isOnline),
.io_isLast(isLast_temp1),
.io_DCIn(DCIn),
.param_pl(`PL),
.param_npl(`NPL),
.param_vendorID(`VENDORID),
.param_moduleID(`MODULEID),
.param_hwVersion(`HWVERSION),
.param_swVersion(`SWVERSION),
.param_serial(`SERIAL),
.LED_PR(LED_PR),
.LED_ERR(LED_ERR),
.out(outInv),
.flt_0(flt_0),
.flt_1(flt_1),
.v24Det(v24Det),
.io_lvdsSlv_downstream_rx_data_out(downstream_rx_data_out),
.io_lvdsSlv_downstream_rx_data_valid(downstream_rx_data_valid),
.io_lvdsSlv_downstream_rx_crc_valid(downstream_rx_crc_valid),
.io_lvdsSlv_downstream_rx_crc_err(downstream_rx_crc_err),
.io_lvdsSlv_upstream_tx_data_ready(upstream_tx_data_ready),
.io_lvdsSlv_upstream_tx_data_in(upstream_tx_data_in),
.io_lvdsSlv_downstream_rx_cdr_err(downstream_rx_cdr_err),
.io_lvdsSlv_upstream_rx_cdr_err(upstream_rx_cdr_err)
);
endmodule

7
src/main/verilog/qei_top.v
View File

@@ -149,7 +149,10 @@ Gowin_PLLO Gowin_PLLO(
.clkin(clock)
);
wire lvds_down_din;
wire lvds_down_dout;
wire lvds_up_din;
wire lvds_up_dout;
TLVDS_OBUF lvds_downstream_out(
.O(lvds_down_dout_p),
@@ -304,6 +307,8 @@ Qei i_qei(
.io_lvdsSlv_downstream_rx_cdr_err(downstream_rx_cdr_err),
.io_lvdsSlv_upstream_rx_cdr_err(upstream_rx_cdr_err),
.param_pl(`PL),
.param_npl(`NPL),
.param_vendorID(`VENDORID),
.param_moduleID(`MODULEID),
.param_hwVersion(`HWVERSION),

7
src/main/verilog/spi_top.v
View File

@@ -149,7 +149,10 @@ Gowin_PLLO Gowin_PLLO(
.clkin(clock)
);
wire lvds_down_din;
wire lvds_down_dout;
wire lvds_up_din;
wire lvds_up_dout;
TLVDS_OBUF lvds_downstream_out(
.O(lvds_down_dout_p),
@@ -291,6 +294,8 @@ SpiSlv i_spiSlv(
.io_isLast(isLast_temp1),
.io_DCIn(DCIn),
.param_pl(`PL),
.param_npl(`NPL),
.param_vendorID(`VENDORID),
.param_moduleID(`MODULEID),
.param_hwVersion(`HWVERSION),