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单双边沿切换 类模式

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RuigeLee
2025-09-22 16:34:53 +08:00
parent 9a93481b68
commit 692188fa2f
1 changed files with 28 additions and 19 deletions
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47
src/main/scala/util/DDFlipFlop.scala
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@@ -3,57 +3,64 @@ package BACK
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
class DDRegInit[T<:Data](init: T, pclk: Clock, nclk: Clock, reset: AsyncReset){ class FDRegInit[T<:Data](init: T, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean){
private val pReg = withClockAndReset(pclk, reset) { RegInit( init ) } private val pReg = withClockAndReset(pclk, reset) { RegInit( init ) }
private val nReg = withClockAndReset(nclk, reset) { RegInit( 0.U.asTypeOf(init) ) } private val nReg = withClockAndReset(nclk, reset) { RegInit( 0.U.asTypeOf(init) ) }
val value: T = (pReg.asUInt ^ nReg.asUInt).asTypeOf(init) val value: T =
if( !mode ){ pReg }
else { (pReg.asUInt ^ nReg.asUInt).asTypeOf(init) }
private val next = WireDefault(value) private val next = WireDefault(value)
def :=(d:T): Unit = { next := d } def :=(d:T): Unit = { next := d }
pReg := (nReg.asUInt ^ next.asUInt).asTypeOf(init) if( !mode ){ pReg := next } else { pReg := (nReg.asUInt ^ next.asUInt).asTypeOf(init) }
nReg := (pReg.asUInt ^ next.asUInt).asTypeOf(init) nReg := (pReg.asUInt ^ next.asUInt).asTypeOf(init)
def apply(): T = value def apply(): T = value
} }
object DDRegInit{ object FDRegInit{
def apply[T<:Data](init: T, pclk: Clock, nclk: Clock, reset: AsyncReset): DDRegInit[T] = { def apply[T<:Data](init: T, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean): FDRegInit[T] = {
new DDRegInit(init, pclk, nclk, reset) new FDRegInit(init, pclk, nclk, reset, mode)
} }
} }
class DDRegNext[T<:Data](d: T, init: T, pclk: Clock, nclk: Clock, reset: AsyncReset ){ class FDRegNext[T<:Data](d: T, init: T, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean ){
private val pReg = withClockAndReset(pclk, reset) { RegInit( init ) } private val pReg = withClockAndReset(pclk, reset) { RegInit( init ) }
private val nReg = withClockAndReset(nclk, reset) { RegInit( 0.U.asTypeOf(init) ) } private val nReg = withClockAndReset(nclk, reset) { RegInit( 0.U.asTypeOf(init) ) }
pReg := (d.asUInt ^ nReg.asUInt).asTypeOf(init) if( !mode ) { pReg := d } else { pReg := (d.asUInt ^ nReg.asUInt).asTypeOf(init) }
nReg := (d.asUInt ^ pReg.asUInt).asTypeOf(init) nReg := (d.asUInt ^ pReg.asUInt).asTypeOf(init)
val value: T = (pReg.asUInt ^ nReg.asUInt).asTypeOf(init) val value: T =
if( !mode ){ pReg }
else { (pReg.asUInt ^ nReg.asUInt).asTypeOf(init) }
def apply(): T = value def apply(): T = value
} }
object DDRegNext{ object FDRegNext{
def apply[T<:Data]( d: T, init: T, pclk: Clock, nclk: Clock, reset: AsyncReset ): DDRegNext[T] = { def apply[T<:Data]( d: T, init: T, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean ): T = {
new DDRegNext(d, init, pclk, nclk, reset ) new FDRegNext(d, init, pclk, nclk, reset, mode ).apply()
} }
} }
class DDShiftRegisters[T<:Data]( in: T, n: Int, init: T, en: Bool, pclk: Clock, nclk: Clock, reset: AsyncReset ){ class FDShiftRegisters[T<:Data]( in: T, n: Int, init: T, en: Bool, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean ){
private val pRegs = withClockAndReset(pclk, reset) { RegInit(VecInit(Seq.fill(n)( init ))) } private val pRegs = withClockAndReset(pclk, reset) { RegInit(VecInit(Seq.fill(n)( init ))) }
private val nRegs = withClockAndReset(nclk, reset) { RegInit(VecInit(Seq.fill(n)( 0.U.asTypeOf(init)))) } private val nRegs = withClockAndReset(nclk, reset) { RegInit(VecInit(Seq.fill(n)( 0.U.asTypeOf(init)))) }
// 移位逻辑：首位采样输入，其他依次移位 // 移位逻辑：首位采样输入，其他依次移位
pRegs(0) := (in.asUInt ^ nRegs(0).asUInt).asTypeOf(init) if( !mode ){ pRegs(0) := in } else { pRegs(0) := (in.asUInt ^ nRegs(0).asUInt).asTypeOf(init) }
for(i <- 1 until n) { for(i <- 1 until n) {
pRegs(i) := (pRegs(i-1).asUInt ^ nRegs(i).asUInt).asTypeOf(init) if( !mode ){ pRegs(i) := pRegs(i-1) }
else { pRegs(i) := (pRegs(i-1).asUInt ^ nRegs(i).asUInt).asTypeOf(init)}
} }
nRegs(0) := (in.asUInt ^ pRegs(0).asUInt).asTypeOf(init) nRegs(0) := (in.asUInt ^ pRegs(0).asUInt).asTypeOf(init)
@@ -62,13 +69,15 @@ class DDShiftRegisters[T<:Data]( in: T, n: Int, init: T, en: Bool, pclk: Clock,
} }
// 输出为 pRegs 与 nRegs 异或 // 输出为 pRegs 与 nRegs 异或
def apply(): Seq[T] = (pRegs zip nRegs).map{ case (a, b) => (a.asUInt ^ b.asUInt).asTypeOf(init) } def apply(): Seq[T] =
if( !mode ){ pRegs }
else (pRegs zip nRegs).map{ case (a, b) => (a.asUInt ^ b.asUInt).asTypeOf(init) }
} }
object DDShiftRegisters{ object FDShiftRegisters{
def apply[T<:Data]( in: T, n: Int, init: T, en: Bool, pclk: Clock, nclk: Clock, reset: AsyncReset ): DDShiftRegisters[T] = { def apply[T<:Data]( in: T, n: Int, init: T, en: Bool, pclk: Clock, nclk: Clock, reset: AsyncReset, mode: Boolean ): Seq[T] = {
new DDShiftRegisters( in, n, init, en, pclk, nclk, reset ) new FDShiftRegisters( in, n, init, en, pclk, nclk, reset, mode ).apply()
} }
} }