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test pass

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This commit is contained in:
RuigeLee
2023-08-07 11:40:14 +08:00
parent a041c7732a
commit 68e0a6a055
5 changed files with 59 additions and 42 deletions
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9
src/main/scala/backBoard/CDR4InBus.scala → src/main/scala/backBoard/CDR4InBus.scala.bk
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@@ -6,16 +6,7 @@ import chisel3.util._
import freechips.rocketchip.util._ import freechips.rocketchip.util._
class CDRData extends Bundle{
val address = UInt(6.W)
val register = UInt(8.W)
val data = UInt(32.W)
val hash = UInt(16.W)
def crcHash = 0.U
def isHashPass = true.B
}
class CDRInBusIO() extends Bundle{ class CDRInBusIO() extends Bundle{

9
src/main/scala/backBoard/CDR4MultiIn.scala
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@@ -8,7 +8,16 @@ import chisel3.util._
import freechips.rocketchip.util._ import freechips.rocketchip.util._
class CDRData extends Bundle{
val address = UInt(6.W)
val register = UInt(8.W)
val data = UInt(32.W)
val hash = UInt(16.W)
def crcHash = 0.U
def isHashPass = true.B
}
class CDR4MultiInIO() extends Bundle{ class CDR4MultiInIO() extends Bundle{
val dat = Input(Bool()) val dat = Input(Bool())

19
src/main/scala/backBoard/SpiSlv.scala
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@@ -35,31 +35,32 @@ class SpiSlv extends Module{
val cent = Wire(new CDR_Master_Interface_Bundle) val cent = Wire(new CDR_Master_Interface_Bundle)
withClockAndReset( io.clk4.asClock, reset ){ withClockAndReset( io.clk4.asClock, reset ){
val centReg = RegInit(0.U.asTypeOf(new CDR_Master_Interface_Bundle)); cent := centReg val centReg = RegInit(0.U.asTypeOf(new CDR_Master_Interface_Bundle)); cent := centReg
val sckShift = ShiftRegisters( io.SCK, 4, false.B, true.B ) val sckShift = ShiftRegisters( io.SCK, 3, false.B, true.B )
val csShift = ShiftRegisters( io.CS, 4, true.B, true.B ) val csShift = ShiftRegisters( io.CS, 3, true.B, true.B )
val mosiShift = ShiftRegisters( io.MOSI, 2, true.B, true.B )
val CDROutValidSetReg = RegInit(false.B); CDROutValidSet := CDROutValidSetReg val CDROutValidSetReg = RegInit(false.B); CDROutValidSet := CDROutValidSetReg
val CDROutValidResetAsync = ShiftRegister( CDROutValidReset, 2, false.B, true.B ) val CDROutValidResetAsync = ShiftRegister( CDROutValidReset, 2, false.B, true.B )
val CDRInValidSetAsync = ShiftRegister( io.CDRIn.valid , 2, false.B, true.B ) val CDRInValidSetAsync = ShiftRegister( io.CDRIn.valid , 2, false.B, true.B )
val CDRInValidResetReg = RegNext(CDRInValidSetAsync & csShift(3) & ~CDROutValidSetReg, false.B); CDRInValidReset := CDRInValidResetReg val CDRInValidResetReg = RegNext(CDRInValidSetAsync & csShift(1) & ~CDROutValidSetReg, false.B); CDRInValidReset := CDRInValidResetReg
when( CDROutValidSetReg & CDROutValidResetAsync ){ when( CDROutValidSetReg & CDROutValidResetAsync ){
CDROutValidSetReg := false.B CDROutValidSetReg := false.B
centReg.op := 1.U centReg.op := 1.U
} .elsewhen( ~csShift(3) & csShift(2) ){ } .elsewhen( ~csShift(2) & csShift(1) ){
CDROutValidSetReg := true.B CDROutValidSetReg := true.B
} }
io.MISO := centReg.asUInt.extract( 6+8+32+2+16-1 ) io.MISO := centReg.asUInt.extract( 6+8+32+2+16-1 )
val sckPosedge = ~sckShift(3) & sckShift(2) val sckPosedge = ~sckShift(2) & sckShift(1)
val sckNegedge = sckShift(3) & ~sckShift(2) val sckNegedge = sckShift(2) & ~sckShift(1)
when( ~csShift(3) ){ when( ~csShift(1) ){
when( sckNegedge ){ when( sckPosedge ){
centReg := Cat(centReg.asUInt( 6+8+32+2+16-2, 0 ), io.MOSI).asTypeOf(new CDR_Master_Interface_Bundle) centReg := Cat(centReg.asUInt( 6+8+32+2+16-2, 0 ), mosiShift(1)).asTypeOf(new CDR_Master_Interface_Bundle)
} }
} .otherwise{ } .otherwise{
when( CDRInValidSetAsync & ~CDROutValidSetReg ){ when( CDRInValidSetAsync & ~CDROutValidSetReg ){

48
src/test/scala/gcd/BackPlaneMstTest.scala
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@@ -5,7 +5,7 @@ import chisel3.util._
class BackPlaneMstTestIO extends Bundle{ class BackPlaneMstTestIO extends Bundle{
val SCK = Input(Bool()) // val SCK = Input(Bool())
val interrupt = Output(Bool()) val interrupt = Output(Bool())
val clk4 = Input( Bool() ) val clk4 = Input( Bool() )
val reset = Input(Bool()) val reset = Input(Bool())
@@ -20,7 +20,7 @@ class BackPlaneMstTestIO extends Bundle{
class BackPlaneMstTest extends RawModule{ class BackPlaneMstTest extends RawModule{
val io: BackPlaneMstTestIO = IO(new BackPlaneMstTestIO) val io: BackPlaneMstTestIO = IO(new BackPlaneMstTestIO)
withClockAndReset( io.SCK.asClock, io.reset.asAsyncReset ){ withClockAndReset( io.clk4.asClock, io.reset.asAsyncReset ){
val dut = Module(new BackBoardMst) val dut = Module(new BackBoardMst)
io.downStreamRespdat := dut.io.downStreamRespdat io.downStreamRespdat := dut.io.downStreamRespdat
@@ -28,41 +28,57 @@ class BackPlaneMstTest extends RawModule{
// dut.io.CS := io.CS // dut.io.CS := io.CS
// io.MISO := dut.io.MISO // io.MISO := dut.io.MISO
// dut.io.MOSI := io.MOSI // dut.io.MOSI := io.MOSI
dut.io.SCK := io.SCK // dut.io.SCK := io.SCK
dut.io.clk4 := io.clk4 dut.io.clk4 := io.clk4
io.interrupt := dut.io.interrupt io.interrupt := dut.io.interrupt
io.req.ready := true.B
val reqDat = RegInit(false.B); dut.io.downStreamReqDat := reqDat
val reqInfo = RegInit(0.U((new CDRData).getWidth.W))
when( io.req.fire ){
reqInfo := io.req.bits.asUInt
reqDat := true.B
} .otherwise{
reqDat := reqInfo.extract( 6+8+32+16-1 )
reqInfo := Cat( reqInfo( 6+8+32+16-2,0 ), 0.U(1.W) )
}
io.spi.ready := true.B io.spi.ready := true.B
val cnt = RegInit(0.U(7.W)) val cnt = RegInit(0.U(7.W))
val spiInfo = Reg( new CDR_Master_Interface_Bundle ) val spiInfo = Reg( new CDR_Master_Interface_Bundle )
val MOSI = RegInit(false.B); dut.io.MOSI := spiInfo.asUInt().extract( 6+8+32+2+16-1 ) dut.io.MOSI := spiInfo.asUInt().extract( 6+8+32+2+16-1 )
val cs = RegInit(true.B); dut.io.CS := cs val cs = RegInit(true.B); dut.io.CS := cs
val sckCnt = RegInit(1.U(2.W)); dut.io.SCK := sckCnt.extract(1) === 1.U
when( ~cs ){
sckCnt := sckCnt + 1.U
}
when( io.spi.fire ){ when( io.spi.fire ){
cs := false.B cs := false.B
cnt := 0.U cnt := 0.U
spiInfo := io.spi.bits spiInfo := io.spi.bits
} .elsewhen( cnt =/= 63.U ){ } .elsewhen( cnt =/= 63.U & sckCnt === "b11".U ){
cnt := cnt + 1.U cnt := cnt + 1.U
spiInfo := Cat(spiInfo.asUInt( 6+8+32+2+16-2, 0 ), dut.io.MISO).asTypeOf(new CDR_Master_Interface_Bundle) spiInfo := Cat(spiInfo.asUInt( 6+8+32+2+16-2, 0 ), dut.io.MISO).asTypeOf(new CDR_Master_Interface_Bundle)
} .elsewhen( cnt === 63.U ){ } .elsewhen( cnt === 63.U & sckCnt === "b11".U ){
cs := true.B cs := true.B
} }
io.req.ready := true.B
val reqDat = RegInit(false.B); dut.io.downStreamReqDat := reqDat
val reqInfo = RegInit(0.U((new CDRData).getWidth.W))
val datCnt = RegInit( 0.U(2.W) )
datCnt := datCnt + 1.U
when( datCnt === "b11".U ) {
when( io.req.fire ){
reqInfo := io.req.bits.asUInt
reqDat := true.B
} .otherwise{
reqDat := reqInfo.extract( 6+8+32+16-1 )
reqInfo := Cat( reqInfo( 6+8+32+16-2,0 ), 0.U(1.W) )
}
}
} }

16
tb/sim_backMst.cpp
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@@ -86,7 +86,7 @@ int main(int argc, char **argv, char **env) {
top->io_reset = 1; top->io_reset = 1;
top->io_SCK = 0; // top->io_SCK = 0;
top->io_clk4 = 0; top->io_clk4 = 0;
while(!Verilated::gotFinish()) { while(!Verilated::gotFinish()) {
@@ -98,11 +98,11 @@ int main(int argc, char **argv, char **env) {
top->io_reset = 0; top->io_reset = 0;
} }
if ( main_time % 400 == 100 ) { // if ( main_time % 400 == 100 ) {
top->io_SCK = 1; // top->io_SCK = 1;
} else if ( main_time % 400 == 300 ) { // } else if ( main_time % 400 == 300 ) {
top->io_SCK = 0; // top->io_SCK = 0;
} // }
if ( main_time % 100 == 10 ) { if ( main_time % 100 == 10 ) {
top->io_clk4 = 1; top->io_clk4 = 1;
@@ -119,7 +119,7 @@ int main(int argc, char **argv, char **env) {
top->io_spi_bits_op = 0x01; top->io_spi_bits_op = 0x01;
top->io_spi_bits_hash = 0x0; top->io_spi_bits_hash = 0x0;
} else if( main_time == 50400 ){ } else if( main_time == 50100 ){
top->io_spi_valid = 0; top->io_spi_valid = 0;
} }
@@ -140,7 +140,7 @@ int main(int argc, char **argv, char **env) {
top->io_spi_bits_op = 0x00; top->io_spi_bits_op = 0x00;
top->io_spi_bits_hash = 0x0; top->io_spi_bits_hash = 0x0;
} else if( main_time == 250400 ){ } else if( main_time == 250100 ){
top->io_spi_valid = 0; top->io_spi_valid = 0;
} }