test pass

src/test/scala/gcd/BackPlaneMstTest.scala

@@ -5,7 +5,7 @@ import chisel3.util._
 
 class BackPlaneMstTestIO extends Bundle{
 
-  val SCK  = Input(Bool())
+  // val SCK  = Input(Bool())
   val interrupt = Output(Bool())
   val clk4            = Input( Bool() )
   val reset = Input(Bool())
@@ -20,7 +20,7 @@ class BackPlaneMstTestIO extends Bundle{
 class BackPlaneMstTest extends RawModule{
   val io: BackPlaneMstTestIO = IO(new BackPlaneMstTestIO)
 
-  withClockAndReset( io.SCK.asClock, io.reset.asAsyncReset ){
+  withClockAndReset( io.clk4.asClock, io.reset.asAsyncReset ){
     val dut = Module(new BackBoardMst)
 
     io.downStreamRespdat := dut.io.downStreamRespdat
@@ -28,41 +28,57 @@ class BackPlaneMstTest extends RawModule{
     // dut.io.CS   := io.CS
     // io.MISO     := dut.io.MISO
     // dut.io.MOSI := io.MOSI
-    dut.io.SCK  := io.SCK
+    // dut.io.SCK  := io.SCK
 
     dut.io.clk4 := io.clk4
     io.interrupt := dut.io.interrupt
 
 
-    io.req.ready := true.B
-    val reqDat = RegInit(false.B); dut.io.downStreamReqDat := reqDat
-    val reqInfo = RegInit(0.U((new CDRData).getWidth.W))
 
-    when( io.req.fire ){
-      reqInfo := io.req.bits.asUInt
-      reqDat := true.B
-    } .otherwise{
-      reqDat := reqInfo.extract( 6+8+32+16-1 )
-      reqInfo := Cat( reqInfo( 6+8+32+16-2,0 ), 0.U(1.W) )
-    }
+
 
     io.spi.ready := true.B
     val cnt = RegInit(0.U(7.W))
     val spiInfo = Reg( new CDR_Master_Interface_Bundle )
-    val MOSI = RegInit(false.B); dut.io.MOSI := spiInfo.asUInt().extract( 6+8+32+2+16-1 )
+    dut.io.MOSI := spiInfo.asUInt().extract( 6+8+32+2+16-1 )
     val cs   = RegInit(true.B);  dut.io.CS   := cs
+    val sckCnt = RegInit(1.U(2.W)); dut.io.SCK := sckCnt.extract(1) === 1.U
+
+    when( ~cs ){
+      sckCnt := sckCnt + 1.U
+    }
 
     when( io.spi.fire ){
       cs := false.B
       cnt := 0.U
       spiInfo := io.spi.bits
-    } .elsewhen( cnt =/= 63.U ){
+    } .elsewhen( cnt =/= 63.U & sckCnt === "b11".U ){
       cnt := cnt + 1.U
       spiInfo := Cat(spiInfo.asUInt( 6+8+32+2+16-2, 0 ), dut.io.MISO).asTypeOf(new CDR_Master_Interface_Bundle)
-    } .elsewhen( cnt === 63.U ){
+    } .elsewhen( cnt === 63.U & sckCnt === "b11".U ){
       cs := true.B
     }
 
+
+
+    io.req.ready := true.B
+    val reqDat = RegInit(false.B); dut.io.downStreamReqDat := reqDat
+    val reqInfo = RegInit(0.U((new CDRData).getWidth.W))
+    val datCnt = RegInit( 0.U(2.W) )
+
+    datCnt := datCnt + 1.U
+
+    when( datCnt === "b11".U ) {
+      when( io.req.fire  ){
+        reqInfo := io.req.bits.asUInt
+        reqDat := true.B
+      } .otherwise{
+        reqDat := reqInfo.extract( 6+8+32+16-1 )
+        reqInfo := Cat( reqInfo( 6+8+32+16-2,0 ), 0.U(1.W) )
+      }      
+    }
+
+
   }