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test pass

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This commit is contained in:
RuigeLee
2023-08-07 11:40:14 +08:00
parent a041c7732a
commit 68e0a6a055
5 changed files with 59 additions and 42 deletions
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9
src/main/scala/backBoard/CDR4InBus.scala → src/main/scala/backBoard/CDR4InBus.scala.bk
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@@ -6,16 +6,7 @@ import chisel3.util._
import freechips.rocketchip.util._
class CDRData extends Bundle{
val address = UInt(6.W)
val register = UInt(8.W)
val data = UInt(32.W)
val hash = UInt(16.W)
def crcHash = 0.U
def isHashPass = true.B
}
class CDRInBusIO() extends Bundle{

9
src/main/scala/backBoard/CDR4MultiIn.scala
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@@ -8,7 +8,16 @@ import chisel3.util._
import freechips.rocketchip.util._
class CDRData extends Bundle{
val address = UInt(6.W)
val register = UInt(8.W)
val data = UInt(32.W)
val hash = UInt(16.W)
def crcHash = 0.U
def isHashPass = true.B
}
class CDR4MultiInIO() extends Bundle{
val dat = Input(Bool())

19
src/main/scala/backBoard/SpiSlv.scala
View File

@@ -35,31 +35,32 @@ class SpiSlv extends Module{
val cent = Wire(new CDR_Master_Interface_Bundle)
withClockAndReset( io.clk4.asClock, reset ){
val centReg = RegInit(0.U.asTypeOf(new CDR_Master_Interface_Bundle)); cent := centReg
val sckShift = ShiftRegisters( io.SCK, 4, false.B, true.B )
val csShift = ShiftRegisters( io.CS, 4, true.B, true.B )
val sckShift = ShiftRegisters( io.SCK, 3, false.B, true.B )
val csShift = ShiftRegisters( io.CS, 3, true.B, true.B )
val mosiShift = ShiftRegisters( io.MOSI, 2, true.B, true.B )
val CDROutValidSetReg = RegInit(false.B); CDROutValidSet := CDROutValidSetReg
val CDROutValidResetAsync = ShiftRegister( CDROutValidReset, 2, false.B, true.B )
val CDRInValidSetAsync = ShiftRegister( io.CDRIn.valid , 2, false.B, true.B )
val CDRInValidResetReg = RegNext(CDRInValidSetAsync & csShift(3) & ~CDROutValidSetReg, false.B); CDRInValidReset := CDRInValidResetReg
val CDRInValidResetReg = RegNext(CDRInValidSetAsync & csShift(1) & ~CDROutValidSetReg, false.B); CDRInValidReset := CDRInValidResetReg
when( CDROutValidSetReg & CDROutValidResetAsync ){
CDROutValidSetReg := false.B
centReg.op := 1.U
} .elsewhen( ~csShift(3) & csShift(2) ){
} .elsewhen( ~csShift(2) & csShift(1) ){
CDROutValidSetReg := true.B
}
io.MISO := centReg.asUInt.extract( 6+8+32+2+16-1 )
val sckPosedge = ~sckShift(3) & sckShift(2)
val sckNegedge = sckShift(3) & ~sckShift(2)
val sckPosedge = ~sckShift(2) & sckShift(1)
val sckNegedge = sckShift(2) & ~sckShift(1)
when( ~csShift(3) ){
when( sckNegedge ){
centReg := Cat(centReg.asUInt( 6+8+32+2+16-2, 0 ), io.MOSI).asTypeOf(new CDR_Master_Interface_Bundle)
when( ~csShift(1) ){
when( sckPosedge ){
centReg := Cat(centReg.asUInt( 6+8+32+2+16-2, 0 ), mosiShift(1)).asTypeOf(new CDR_Master_Interface_Bundle)
}
} .otherwise{
when( CDRInValidSetAsync & ~CDROutValidSetReg ){