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RuigeLee
2024-10-29 11:21:04 +08:00
parent 8068a31e77
commit 683b6cad92
7 changed files with 268 additions and 44 deletions
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65
Makefile
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@@ -60,44 +60,53 @@ test:
sw:
# riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs \
# -I ./tb/sw/ -I ./tb/sw/src -I ./tb/sw/axi_gpio -I ./tb/sw/axi_uart -I ./tb/sw/axi_timer \
# -c ./tb/sw/src/main.c \
# -o ./tb/sw/build/main.o
# riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs \
# -I ./tb/sw/ -I ./tb/sw/src -I ./tb/sw/axi_gpio -I ./tb/sw/axi_uart -I ./tb/sw/axi_timer \
# -c ./tb/sw/axi_uart/uart.c \
# -o ./tb/sw/build/uart.o
riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-c ./tb/sw/src/mstStartup.S \
-o ./tb/sw/build/mstStartup.o
riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-c ./tb/sw/src/startup.S \
-o ./tb/sw/build/startup.o
riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-c ./tb/sw/src/main.S \
-o ./tb/sw/build/main.o
-c ./tb/sw/src/mstMain.S \
-o ./tb/sw/build/mstMain.o
riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
-T ./tb/sw/linker.lds \
./tb/sw/build/startup.o \
./tb/sw/build/main.o \
-o ./tb/sw/build/test.elf
./tb/sw/build/mstStartup.o \
./tb/sw/build/mstMain.o \
-o ./tb/sw/build/mstTest.elf
riscv64-unknown-elf-objcopy -O binary ./tb/sw/build/test.elf ./tb/sw/build/test.bin
riscv64-unknown-elf-objcopy -O binary ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.bin
# riscv64-unknown-elf-objdump -h ./tb/sw/build/test.elf > ./tb/sw/build/test.dump
riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/test.elf > ./tb/sw/build/test.dump
riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/mstTest.elf > ./tb/sw/build/mstTest.dump
riscv64-unknown-elf-objcopy -O verilog ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.verilog
sed -i 's/@800/@000/g' ./tb/sw/build/mstTest.verilog
# riscv64-unknown-elf-objcopy --add-section .trap_entry=./tb/sw/build/test.bin ./tb/sw/build/test.elf ./tb/sw/build/test_with_section.elf
# riscv64-unknown-elf-readelf -a ./tb/sw/build/test.elf
# riscv64-unknown-elf-objcopy --add-section .trap_entry=./tb/sw/build/test.bin ./tb/sw/build/test.elf ./tb/sw/build/test_with_section.elf
riscv64-unknown-elf-objcopy -O verilog ./tb/sw/build/test.elf ./tb/sw/build/test.verilog
sed -i 's/@800/@000/g' ./tb/sw/build/test.verilog
riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-c ./tb/sw/src/slvStartup.S \
-o ./tb/sw/build/slvStartup.o
riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-c ./tb/sw/src/slvMain.S \
-o ./tb/sw/build/slvMain.o
riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
-T ./tb/sw/linker.lds \
./tb/sw/build/slvStartup.o \
./tb/sw/build/slvMain.o \
-o ./tb/sw/build/slvTest.elf
riscv64-unknown-elf-objcopy -O binary ./tb/sw/build/slvTest.elf ./tb/sw/build/slvTest.bin
riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/slvTest.elf > ./tb/sw/build/slvTest.dump
riscv64-unknown-elf-objcopy -O verilog ./tb/sw/build/slvTest.elf ./tb/sw/build/slvTest.verilog
sed -i 's/@800/@000/g' ./tb/sw/build/slvTest.verilog
fst:
gtkwave ./tb/build/wave.fst &