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发送改用标志头锁时钟通道方案

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This commit is contained in:
RuigeLee
2024-09-23 16:44:44 +08:00
parent f05e320236
commit 6750593b48
1 changed files with 38 additions and 6 deletions
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44
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -14,6 +14,7 @@ class CDRInIO extends Bundle{
abstract class CDRInBase extends Module{ abstract class CDRInBase extends Module{
def sampleRate: Int = 4 def sampleRate: Int = 4
// require( sampleRate == 4 )
// require( (sampleRate % 2) == 1 ) // require( (sampleRate % 2) == 1 )
@@ -23,10 +24,41 @@ abstract class CDRInBase extends Module{
} }
trait CDRInOverSample{ this: CDRInBase => trait CDRInOverSample{ this: CDRInBase =>
val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate-1 ) } val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
val arbResult = VecInit(sampleReg).count( (x:Bool) => (x === true.B) ) > ((sampleRate-1) / 2).U // val arbResult = VecInit(sampleReg).count( (x:Bool) => (x === true.B) ) > ((sampleRate-1) / 2).U
val syncSerDat = ShiftRegister( arbResult, 2 )
val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) }
val arbSel = Reg(UInt( log2Ceil(sampleRate).W ))
val isArbLock = RegInit(false.B)
for( i <- 0 until sampleRate ){
arbShiftData(i) := Cat( arbShiftData(i)(22,0), RegNext(sampleReg(i)) )
when( arbShiftData(i) === "h555555".U & ~isArbLock ){
isArbLock := true.B
arbSel := i.U
}
}
when( ( 0 until sampleRate ).map{ i => (arbShiftData(i) === 0.U) }.reduce(_&_) ){
isArbLock := false.B
}
// val arbResult =
// (sampleReg(3) & sampleReg(2) & sampleReg(1)) |
// (sampleReg(3) & sampleReg(2) & sampleReg(0)) |
// (sampleReg(3) & sampleReg(1) & sampleReg(0)) |
// (sampleReg(2) & sampleReg(1) & sampleReg(0))
val syncSerDat = ShiftRegister(
Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } )
, 2 )
} }
@@ -66,7 +98,7 @@ trait CDRInAxis{ this: CDRInBase =>
stateNext := stateNext :=
Mux1H(Seq( Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 7.U) & (shiftData === ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE (stateCurr === STATE_IDLE) -> ( Mux( /*(byteCnt === 7.U) &*/ (bitCnt === 7.U) & (shiftData === ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_HEADER ) ), (stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_HEADER ) ),
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 7.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 7.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD
(stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 3.U) & (bitCnt === 7.U), STATE_IDLE, STATE_CRC )), //CRC (stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 3.U) & (bitCnt === 7.U), STATE_IDLE, STATE_CRC )), //CRC
@@ -88,8 +120,8 @@ trait CDRInAxis{ this: CDRInBase =>
byteCnt := 1.U byteCnt := 1.U
} .elsewhen( bitCnt === 7.U ){ } .elsewhen( bitCnt === 7.U ){
when( stateCurr === STATE_IDLE ){ when( stateCurr === STATE_IDLE ){
byteCnt := Mux( byteCnt =/= 7.U & shiftData === ETH_PRE, byteCnt + 1.U, 0.U)//keep align, align failed or SFD pass byteCnt := Mux( /*byteCnt =/= 7.U &*/ shiftData === ETH_PRE, byteCnt + 1.U, 0.U)//keep align, align failed or SFD pass
assert( byteCnt <= 7.U ) /*assert( byteCnt <= 7.U )*/
} .elsewhen( stateCurr === STATE_HEADER ){ } .elsewhen( stateCurr === STATE_HEADER ){
byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U ) byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
assert( byteCnt <= (HeaderByte-1).U ) assert( byteCnt <= (HeaderByte-1).U )