From 65c5aba8ce63fb4b7ade59f6a1ee342f4f342762 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 29 Apr 2025 17:48:57 +0800 Subject: [PATCH] =?UTF-8?q?=20=E5=AE=8C=E6=88=90=E6=8E=A2=E9=92=88?= =?UTF-8?q?=E5=92=8C=E7=B4=A2=E5=BC=95?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/MasterParser.scala | 6 +- src/main/scala/backBoard/shin/ShinTop.scala | 4 +- .../scala/backBoard/shin/SlaveParser.scala | 26 ++++-- .../scala/backBoard/shin/SlaveRecParser.scala | 6 +- .../scala/backBoard/shin/SlaveSendGen.scala | 8 +- tb/shinTest/ShinTopTb.v | 89 +++++++++++++++---- 6 files changed, 103 insertions(+), 36 deletions(-) diff --git a/src/main/scala/backBoard/shin/MasterParser.scala b/src/main/scala/backBoard/shin/MasterParser.scala index 16ab85e..4757d67 100644 --- a/src/main/scala/backBoard/shin/MasterParser.scala +++ b/src/main/scala/backBoard/shin/MasterParser.scala @@ -23,7 +23,7 @@ class MasterParserIO extends Bundle{ val rxEnq = Output( Bool()) val txDeq = Output( Bool()) - val trigAddr = Input( Vec(2, UInt(15.W)) ) + // val trigAddr = Input( Vec(2, UInt(15.W)) ) val timeStamp = Input(UInt(64.W)) @@ -119,8 +119,8 @@ abstract class MasterParserBase extends Module{ - io.rxEnq := io.trigAddr(0) === txCnt & io.downOut.fire - io.txDeq := io.trigAddr(1) === (rxCnt + 1.U) & io.upIn.fire + io.rxEnq := io.downOut.fire & io.downOut.bits.tlast + io.txDeq := io.upIn.fire & io.upIn.bits.tlast diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index 42cf6cd..90957ec 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -231,8 +231,8 @@ trait ShinTopMaster{ this: ShinTopBase => masterParser.io.req := io.req io.rsp := masterParser.io.rsp - masterParser.io.trigAddr(0) := "hff".U - masterParser.io.trigAddr(1) := "hff".U + // masterParser.io.trigAddr(0) := "hff".U + // masterParser.io.trigAddr(1) := "hff".U masterParser.io.timeStamp := io.timeStamp } diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 9e65fbd..6cf8fa1 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -76,7 +76,8 @@ abstract class SlaveParserBase extends Module{ val downSendGen = Module(new SlaveSendGen) val upSendGen = Module(new SlaveSendGen) - val isReadyToProbe = RegInit(false.B) + val isReadyToProbe = RegInit(false.B) + val isAckProbe = RegInit(false.B) val isLastDevice: Bool = RegInit(true.B) val isDeviceModified: Bool = RegInit(true.B) @@ -107,6 +108,9 @@ abstract class SlaveParserBase extends Module{ } .elsewhen( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){//下行来了一个普通包 isDownSendPend := true.B downFrameInfo := downRecParser.io.frameReq.bits + } .elsewhen( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){//下行来了一个嗅探包 + isDownSendPend := true.B + downFrameInfo := downRecParser.io.frameReq.bits } when( upSendGen.io.frameReq.fire ){ @@ -118,8 +122,8 @@ abstract class SlaveParserBase extends Module{ downSendGen.io.frameReq.valid := - isDownSendPend & downRecParser.io.subMsgReq.fire //| 下行转发 - //isDownSendProbe //下行探针 + isDownSendPend & downFrameInfo.frameStyle === FRAME_STYLE_COMMON & downRecParser.io.subMsgReq.fire | //下行转发 + isDownSendPend & downFrameInfo.frameStyle === FRAME_STYLE_PROBE //下行探针 // assert( OneHot(isDownSendPend, isDownSendProbe) ) @@ -136,13 +140,13 @@ abstract class SlaveParserBase extends Module{ upSendGen.io.frameReq.valid := isUpSendPend & upRecParser.io.subMsgReq.fire | //上行转发 - isReadyToProbe // 上行探针 + isAckProbe // 上行探针 - assert( ~(isUpSendPend & isReadyToProbe), "Assert Failed, Check Softwave, Probe is Sent while transfering!\n" ) + assert( ~(isUpSendPend & isAckProbe), "Assert Failed, Check Softwave, Probe is Sent while transfering!\n" ) upSendGen.io.frameReq.bits := Mux1H(Seq( isUpSendPend -> upFrameInfo, //上行转发 - isReadyToProbe -> upFrameProbeInfo, //上行探针 + isAckProbe -> upFrameProbeInfo, //上行探针 )) @@ -616,8 +620,8 @@ trait SlaveParserSync{ this: SlaveParserBase => trait SlaveParserProbe{ this: SlaveParserBase => - val ProbeRecAim = 20000.U - val probeRecCnt = RegInit(0.U(32.W)) + val ProbeRecAim = 31.U + val probeRecCnt = RegInit(0.U(5.W)) val isWatchDogOverflow = probeRecCnt === ProbeRecAim @@ -634,7 +638,11 @@ trait SlaveParserProbe{ this: SlaveParserBase => isReadyToProbe := false.B } - + when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //下行来了一个嗅探包 + isAckProbe := true.B + } .elsewhen( upSendGen.io.frameReq.fire & upSendGen.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行发送回复嗅探包 + isAckProbe := false.B + } diff --git a/src/main/scala/backBoard/shin/SlaveRecParser.scala b/src/main/scala/backBoard/shin/SlaveRecParser.scala index 1edf61c..d62ebd7 100644 --- a/src/main/scala/backBoard/shin/SlaveRecParser.scala +++ b/src/main/scala/backBoard/shin/SlaveRecParser.scala @@ -83,7 +83,7 @@ class SlaveRecParser extends Module{ - io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_PAYLOAD_INDEX_STYLE) + io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext =/= STATE_HEADER) val frameHeader = Reg(new FrameHeader) io.frameReq.bits.frameLenAim := frameHeader.frameLenAim io.frameReq.bits.frameStyle := frameHeader.frameStyle @@ -172,8 +172,8 @@ class SlaveRecParser extends Module{ ( stateCurr === STATE_HEADER ) -> Mux( isShortRx, STATE_ERROR, Mux( lengthCnt =/= (4-1).U, STATE_HEADER, MuxCase( STATE_ERROR, Array( - ( io.rec.bits.tdata(1,0) === FRAME_STYLE_COMMON ) -> STATE_PAYLOAD_INDEX_STYLE, - ( io.rec.bits.tdata(1,0) === FRAME_STYLE_PROBE ) -> STATE_CRC, + ( frameHeader.frameStyle === FRAME_STYLE_COMMON ) -> STATE_PAYLOAD_INDEX_STYLE, + ( frameHeader.frameStyle === FRAME_STYLE_PROBE ) -> STATE_CRC, )) ) ), diff --git a/src/main/scala/backBoard/shin/SlaveSendGen.scala b/src/main/scala/backBoard/shin/SlaveSendGen.scala index f9771b4..3b51d47 100644 --- a/src/main/scala/backBoard/shin/SlaveSendGen.scala +++ b/src/main/scala/backBoard/shin/SlaveSendGen.scala @@ -31,6 +31,8 @@ class SlaveSendGen extends Module{ val crc = Module(new crc32_8) + val FRAME_STYLE_COMMON = 0.U + val FRAME_STYLE_PROBE = 1.U val STATE_IDLE = 0.U //空闲 val STATE_FRAME_HEADER = 1.U //长度/ /保留2bits //包类型 @@ -107,7 +109,11 @@ class SlaveSendGen extends Module{ stateNext := Mux1H(Seq( (stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ), - (stateCurr === STATE_FRAME_HEADER) -> Mux( lengthCnt === (4-1).U, Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ), STATE_FRAME_HEADER), + (stateCurr === STATE_FRAME_HEADER) -> Mux( lengthCnt === (4-1).U, Mux( + frameInfo.frameStyle === FRAME_STYLE_COMMON, + Mux(io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR), + STATE_CRC ), + STATE_FRAME_HEADER), (stateCurr === STATE_SUBMSG_HEADER) -> Mux( lengthCnt === (8-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), (stateCurr === STATE_SUBMSG_DATA) -> Mux( lengthCnt === subMsgInfoSel.length-1.U, //已经发送完成该子报文 diff --git a/tb/shinTest/ShinTopTb.v b/tb/shinTest/ShinTopTb.v index 7e82eda..718b18a 100644 --- a/tb/shinTest/ShinTopTb.v +++ b/tb/shinTest/ShinTopTb.v @@ -275,7 +275,7 @@ ShinTop s_ShinTop_slv2( .io_upIn_bits_tuser (io_up_bits_tuser[3]), .io_upOut_ready (io_up_ready[2]), .io_upOut_valid (io_up_valid[2]), - .io_upOut_bits_tdata (io_up_bits_tdata[31:24]), + .io_upOut_bits_tdata (io_up_bits_tdata[23:16]), .io_upOut_bits_tlast (io_up_bits_tlast[2]), .io_upOut_bits_tuser (io_up_bits_tuser[2]), @@ -461,24 +461,7 @@ end reg [7:0] dataBuf[0:2047]; initial begin - dataBuf[0] = 8'h00; - dataBuf[1] = 8'ha0;//heeader length 10 - dataBuf[2] = 8'h00; - dataBuf[3] = 8'h00; - //子报文 - //设置顺序地址 - dataBuf[4] = 8'h0; //设备索引 - dataBuf[5] = 8'h0; //设备索引、类型 - dataBuf[6] = $random; //地址 - dataBuf[7] = $random; //地址 - dataBuf[8] = 8'hd0; //命令d 负载长度2 - dataBuf[9] = 8'd02; //负载长度2 - dataBuf[10] = 8'h0; //工作计数0 - dataBuf[11] = 8'h0; //工作计数0 - - dataBuf[12] = 8'h0; //负载 - dataBuf[13] = 8'h0; //负载 end @@ -501,8 +484,78 @@ end initial begin + + //嗅探 #1000 + dataBuf[0] = 8'h00; + dataBuf[1] = 8'h01;//heeader length 0 嗅探包1 + dataBuf[2] = 8'h00; + dataBuf[3] = 8'h00; + + //无子报文 + + //装填sram + for( integer i = 0; i < 4; i = i + 1 ) begin + @(posedge clock) #3 + sram_w_0_enw = 1'b1; + sram_w_0_addrw = i; + sram_w_0_dataw = dataBuf[i]; + end + + @(posedge clock) #3 + sram_w_0_enw = 1'b0; + sram_w_0_addrw = 15'h0; + sram_w_0_dataw = 8'h0; + + //提交SM + @(posedge clock) #3 + txCmf = 1'b1; + @(posedge clock) #3 + txCmf = 1'b0; + + //发布请求 + @(posedge clock) #3 + req_valid = 1'b1; + req_bits_txAddr = 0; + req_bits_rxAddr = 0; + req_bits_length = 4; + + @(posedge clock) #3 + req_valid = 1'b0; + + + + + + + + + + // 顺序索引 + #10000 + + dataBuf[0] = 8'h00; + dataBuf[1] = 8'ha0;//heeader length 10 + dataBuf[2] = 8'h00; + dataBuf[3] = 8'h00; + + //子报文 + //设置顺序地址 + dataBuf[4] = 8'h0; //设备索引 + dataBuf[5] = 8'h0; //设备索引、类型 + dataBuf[6] = $random; //地址 + dataBuf[7] = $random; //地址 + dataBuf[8] = 8'hd0; //命令d 负载长度2 + dataBuf[9] = 8'd02; //负载长度2 + dataBuf[10] = 8'h0; //工作计数0 + dataBuf[11] = 8'h0; //工作计数0 + + dataBuf[12] = 8'h0; //负载 + dataBuf[13] = 8'h0; //负载 + + + for( integer i = 0; i < 14; i = i + 1 ) begin @(posedge clock) #3 sram_w_0_enw = 1'b1;