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修改同步点调整逻辑

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This commit is contained in:
Ruige Lee
2025-08-28 15:53:17 +08:00
parent d4c793bf0b
commit 659ab14fab
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/backBoard/shin/Interface.scala
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@@ -973,7 +973,7 @@ trait InterfaceSync{ this: InterfaceBase =>
val syncResetCnt = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) } //空开第0位
when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
when( cReg.syncPoint >= cReg.recoTimeStamp ){ //时间到达sync0时间点
syncSign(0) := true.B
syncPoint := syncPoint + cReg.syncPeroid
} .elsewhen( ~cReg.syncCfg(4+0) & syncResetCnt(0) === cReg.syncWidth(0) ){
@@ -984,7 +984,7 @@ trait InterfaceSync{ this: InterfaceBase =>
for( i <- 1 until 4 ) {
when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
when( cReg.syncPoint >= cReg.recoTimeStamp ){ //时间到达sync0时间点
syncOffsetCnt(i) := 0.U
} .elsewhen( syncOffsetCnt(i) < cReg.syncOffset(i) ){
syncOffsetCnt(i) := syncOffsetCnt(i) + 1.U