展开文件结构

src/main/scala/backBoard/shin/Interface.scala

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+package BACK
+
+import chisel3._
+import chisel3.util._
+
+class InterfaceIO extends Module{
+
+}
+
+abstract class InterfaceBase extends Module{
+  val io: InterfaceIO = IO(new InterfaceIO)
+
+
+}
+
+
+class Interface extends InterfaceBase{
+
+}

src/main/scala/backBoard/shin/MasterParser.scala

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+package BACK
+
+import chisel3._
+import chisel3.util._
+
+class MasterParserIO extends Module{
+
+}
+
+abstract class MasterParserBase extends Module{
+  val io: MasterParserIO = IO(new MasterParserIO)
+
+
+}
+
+
+class MasterParser extends MasterParserBase{
+
+}

src/main/scala/backBoard/shin/ShareSRAM.scala

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+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+class ShareSRAMDP extends BlackBox with HasBlackBoxInline {
+
+  class ShareSRAMDPIO extends Bundle{
+
+      val addrA  = Input(UInt(15.W))
+      val datawA  = Input( UInt(8.W) )
+      val datarA  = Output( UInt(8.W) )
+      val enwA    = Input(Bool())
+      val enrA    = Input(Bool())
+      val clockA  = Input(Bool())
+
+
+      val addrB = Input(UInt(15.W))
+      val datawB = Input( UInt(8.W) )
+      val datarB = Output( UInt(8.W) )
+      val enwB   = Input(Bool())
+      val enrB   = Input(Bool())
+      val clockB = Input(Bool())
+
+  }
+  val io: MirrorSRAMDPIO = IO(new MirrorSRAMDPIO)
+
+ setInline("MirrorSRAMDP.v",
+              """
+      | module MirrorSRAMDP(
+      |  	input [7:0]  datawA,
+      |  	input [14:0]   addrA,
+      |  	input enwA,
+      |  	input enrA,
+      |  	output [7:0] datarA,
+      |  	input clockA,
+      |
+      |  	input [7:0]  datawB,
+      |  	input [14:0]   addrB,
+      |  	input enwB,
+      |  	input enrB,
+      |  	output [7:0] datarB,
+      |  	input clockB
+      |  );
+      |  
+      |  reg [7:0] mem[0:32767];
+      |  reg [7:0] data_outa_reg = 8'b0;
+      |  reg [7:0] data_outb_reg = 8'b0;
+      |
+      |  assign datarA = data_outa_reg;
+      |  assign datarB = data_outb_reg;
+      |
+      |  always@( posedge clockA ) begin
+      |    if( enrA ) begin
+      |    end
+      |
+      |    if( enwA ) begin
+      |      mem[addrA] <= datawA;
+      |    end else begin
+      |      data_outa_reg <= mem[addrA];
+      |    end
+      |  end
+      |
+      |
+      |  always@( posedge clockB ) begin
+      |    if(enrB) begin
+      |    end
+      |
+      |    if( enwB ) begin
+      |      mem[addrB] <= datawB;
+      |    end else begin
+      |      data_outb_reg <= mem[addrB];
+      |    end
+      |  end
+      |
+      |  initial begin
+      |     for( integer i = 0; i < 32768; i = i + 1 ) begin
+      |       mem[i] = $random;
+      |     end
+      |  end
+      |
+      |
+      |endmodule
+    """.stripMargin)
+}

src/main/scala/backBoard/shin/ShinTop.scala

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+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+class ShinTopIO extends Bundle{
+	val clk8x = Input(Bool())
+	val modeSel = Input(Bool())\
+	
+  val dDatIn   = Input(Bool())
+  val dDatOut  = Output(Bool())
+  val uDatIn   = Input(Bool())
+  val uDatOut  = Output(Bool())
+
+	val qspi = 
+	val interrupt = Output(Bool())
+	val ctrl      = Input(UInt(4.W))
+}
+
+
+
+class ShinTop extends Module{
+  val io: ShinTopIO = IO(new ShinTopIO)
+
+  val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
+	val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
+
+	val slaveParser  = Module(new SlaveParser )
+	val masterParser = Module(new MasterParser)
+
+	val sram = Module(new ShareSRAMDP)
+
+	val interface = Module(new Interface)
+
+
+  sram.io.addrA   := Input(UInt(15.W))
+  sram.io.datawA  := Input( UInt(8.W) )
+  sram.io.datarA  := Output( UInt(8.W) )
+  sram.io.enwA    := Input(Bool())
+  sram.io.enrA    := Input(Bool())
+  sram.io.clockA  := Input(Bool())
+
+  sram.io.addrB  := Input(UInt(15.W))
+  sram.io.datawB := Input( UInt(8.W) )
+  sram.io.datarB := Output( UInt(8.W) )
+  sram.io.enwB   := Input(Bool())
+  sram.io.enrB   := Input(Bool())
+  sram.io.clockB := Input(Bool())
+
+
+
+
+}

src/main/scala/backBoard/shin/SlaveParser.scala

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+package BACK
+
+import chisel3._
+import chisel3.util._
+
+class SlaveParserIO extends Module{
+
+}
+
+abstract class SlaveParserBase extends Module{
+  val io: SlaveParserIO = IO(new SlaveParserIO)
+
+
+}
+
+
+class SlaveParser extends SlaveParserBase{
+
+}