展开文件结构
This commit is contained in:
Ruige Lee
586
src/main/scala/backBoard/shin/ShinSlv.scala.bk
Normal file
586
src/main/scala/backBoard/shin/ShinSlv.scala.bk
Normal file
@@ -0,0 +1,586 @@
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package BACK
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import chisel3._
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import chisel3.util._
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class ShinSlvIO_Bundle extends Bundle{
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val isOnline = Output(Bool())
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val isLast = Input(Bool())
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val DCIn = Input(Bool())
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val downSer = new Bundle{
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val out = Output(Bool())
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val in = Input(Bool())
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}
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val upSer = new Bundle{
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val out = Output(Bool())
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val in = Input(Bool())
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}
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val overCLK = Input(Bool())
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}
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abstract class ShinSlvPhyBase extends Module{
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val io: ShinSlvIO_Bundle = IO(new ShinSlvIO_Bundle)
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val downStreamCdrOut = Module(new CDROut with chisel3.util.experimental.InlineInstance)
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val downStreamCdrIn = Module(new CDRIn with chisel3.util.experimental.InlineInstance)
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val upStreamCdrOut = Module(new CDROut with chisel3.util.experimental.InlineInstance)
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val upStreamCdrIn = Module(new CDRIn with chisel3.util.experimental.InlineInstance)
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io.downSer.out := downStreamCdrOut.io.serDat
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downStreamCdrIn.io.serDat := io.downSer.in
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downStreamCdrIn.io.overCLK := io.overCLK
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io.upSer.out := upStreamCdrOut.io.serDat
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upStreamCdrIn.io.serDat := io.upSer.in
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upStreamCdrIn.io.overCLK := io.overCLK
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io.isOnline := true.B
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val downRegTemp = Reg(Vec( 32, UInt(8.W) ))
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val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))
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val headByte = (new Header_Info_Bundle).getWidth/8
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require( headByte == 8 )
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require( headByte > 4, "At Least 4 more additional cycles to ensure CRC Failure boardcast to next nodes!\n")
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val OpInitByte = 8
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val OpBoardCastByte = 16
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val OpUniCastByte = 32
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val maxLocalByte = OpInitByte max OpBoardCastByte max OpUniCastByte
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val downForwardFifo = Module( new Queue( new AXIS_Bundle(8), 8 + headByte + 4 ) with chisel3.util.experimental.InlineInstance)
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val upForwardFifo = Module( new Queue( new AXIS_Bundle(8), headByte + maxLocalByte + 4 ) with chisel3.util.experimental.InlineInstance) //4 is reserve
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val isLastDevice = Wire(Bool())
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}
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trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
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val DownRecvStateIdle = 0.U
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val DownRecvStateOHead = 1.U
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val DownRecvStateSData = 2.U
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val DownRecvStateFData = 3.U
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val DownRecvStateCRC = 4.U
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val downOldHead = Reg( new Header_Info_Bundle )
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val downNewHead = Reg( new Header_Info_Bundle )
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val downNewHeadShift = Reg( new Header_Info_Bundle )
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val downPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance)
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downStreamCdrIn.io.axis <> downPendBuf.io.enq
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val downRecvStateNext = Wire( UInt(3.W) )
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val downRecvStateCurr = RegNext( downRecvStateNext, 0.U )
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val downRecvCnt = Reg(UInt(10.W))
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val downLocalDataByte = RegEnable(
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Mux1H(Seq(
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( downOldHead.asUInt(3,0) === 0.U) -> OpInitByte.U, ( downOldHead.asUInt(3,0) === 1.U) -> OpBoardCastByte.U, ( downOldHead.asUInt(3,0) === 2.U) -> OpUniCastByte.U,
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)), downRecvStateCurr === DownRecvStateOHead & downPendBuf.io.deq.fire & downRecvCnt === 3.U) //Timing Opt
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val isDownStreamError = RegInit( false.B )
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val downForwardDataByte = downNewHead.length
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val isLastDevice: Bool
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downRecvStateNext := Mux1H(Seq(
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(downRecvStateCurr === DownRecvStateIdle ) -> Mux( downPendBuf.io.deq.valid, DownRecvStateOHead, DownRecvStateIdle ),
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(downRecvStateCurr === DownRecvStateOHead) -> Mux( downPendBuf.io.deq.fire, Mux( ~downPendBuf.io.deq.bits.tlast, Mux(downRecvCnt === ((headByte)).U, DownRecvStateSData, DownRecvStateOHead), DownRecvStateIdle ), DownRecvStateOHead),
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(downRecvStateCurr === DownRecvStateSData) -> Mux( downPendBuf.io.deq.fire, Mux( ~downPendBuf.io.deq.bits.tlast, Mux(downRecvCnt === (downLocalDataByte ), Mux( downRecvCnt === (downOldHead.length - 1.U), DownRecvStateCRC, DownRecvStateFData ), DownRecvStateSData), DownRecvStateIdle ), DownRecvStateSData),
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(downRecvStateCurr === DownRecvStateFData) -> Mux( downPendBuf.io.deq.fire, Mux( ~downPendBuf.io.deq.bits.tlast, Mux(downRecvCnt === (downForwardDataByte ) , DownRecvStateCRC, DownRecvStateFData), DownRecvStateIdle ), DownRecvStateFData),
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(downRecvStateCurr === DownRecvStateCRC ) -> Mux( downPendBuf.io.deq.fire & downPendBuf.io.deq.bits.tlast, DownRecvStateIdle, DownRecvStateCRC ),
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))
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when( downRecvStateCurr =/= downRecvStateNext ){
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downRecvCnt := 1.U
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} .elsewhen( downPendBuf.io.deq.fire ){
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downRecvCnt := downRecvCnt + 1.U
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}
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//---------------
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when( downRecvStateCurr === DownRecvStateOHead & downPendBuf.io.deq.fire ){
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downOldHead := Cat( downOldHead.asUInt.tail(8), downPendBuf.io.deq.bits.tdata ).asTypeOf(new Header_Info_Bundle)
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}
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//---------------
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val isDownNewHeadCreated = downRecvStateCurr === DownRecvStateSData & downRecvStateNext === DownRecvStateFData //新头是由老头产生，担忧会欠拍
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when( isDownNewHeadCreated ){
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downNewHead.length := Mux( downOldHead.length >= downLocalDataByte, downOldHead.length - downLocalDataByte, 0.U )
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downNewHead.operator := downOldHead.operator
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downNewHead.param := downOldHead.param
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}
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when( downRecvStateCurr === DownRecvStateSData & downPendBuf.io.deq.fire ){
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downRegTemp(downRecvCnt-1.U) := downPendBuf.io.deq.bits.tdata
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}
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//---------------
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downForwardFifo.io.enq.valid :=
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downRecvStateCurr === DownRecvStateFData & downPendBuf.io.deq.fire & ~isLastDevice
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downForwardFifo.io.enq.bits.tdata := downPendBuf.io.deq.bits.tdata
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downForwardFifo.io.enq.bits.tuser := downPendBuf.io.deq.bits.tuser
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downForwardFifo.io.enq.bits.tlast := downRecvCnt === (downForwardDataByte) | downPendBuf.io.deq.bits.tlast
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downPendBuf.io.deq.ready :=
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(downRecvStateCurr === DownRecvStateOHead) |
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(downRecvStateCurr === DownRecvStateSData) |
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(downRecvStateCurr === DownRecvStateFData) |
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(downRecvStateCurr === DownRecvStateCRC )
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when( downRecvStateCurr === DownRecvStateIdle & downRecvStateNext === DownRecvStateOHead){
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isDownStreamError := false.B
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} .elsewhen( downForwardFifo.io.enq.fire & downForwardFifo.io.enq.bits.tuser ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvStateNext === DownRecvStateIdle ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateSData & downRecvStateNext === DownRecvStateIdle ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateFData & downRecvStateNext === DownRecvStateIdle ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateCRC & downPendBuf.io.deq.fire & downPendBuf.io.deq.bits.tlast & downRecvCnt =/= 4.U ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
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} .elsewhen( isDownNewHeadCreated & downOldHead.length < downLocalDataByte ){ //本包的负载不能满足本级数据需求，传输错误
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
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} .elsewhen( isDownNewHeadCreated & isLastDevice & downOldHead.length =/= downLocalDataByte ){
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printf("Warning, Wrong Package Received in DownStream, SoftWare Check!\n")
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}
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assert( ~(downRecvStateCurr === DownRecvStateFData & ~downForwardFifo.io.enq.ready), "Assert Failed, downStream Forward Fifo is OverFlow!" )
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}
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trait ShinSlvPhyDownStreamSend{ this: ShinSlvPhyBase =>
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val DownSendStateIdle = 0.U
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val DownSendStateNHead = 1.U
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val DownSendStateFData = 2.U
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val downSendCnt = Reg(UInt(10.W))
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val isDownNewHeadCreated: Bool
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val isLastDevice: Bool
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val downForwardDataByte: UInt
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val downNewHead: Header_Info_Bundle
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val downNewHeadShift: Header_Info_Bundle
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val isDownStreamError: Bool
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val downSendStateNext = Wire( UInt(3.W) )
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val downSendStateCurr = RegNext( downSendStateNext, 0.U )
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downSendStateNext := Mux1H(Seq(
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( downSendStateCurr === DownSendStateIdle ) -> Mux( isDownNewHeadCreated & ~isLastDevice, DownSendStateNHead, DownSendStateIdle ),
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( downSendStateCurr === DownSendStateNHead ) -> Mux( downSendCnt === ((headByte)).U & downStreamCdrOut.io.axis.fire, DownSendStateFData, DownSendStateNHead ),
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( downSendStateCurr === DownSendStateFData ) -> Mux( downSendCnt === (downForwardDataByte ) & downStreamCdrOut.io.axis.fire, DownSendStateIdle, DownSendStateFData),
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))
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when( downSendStateCurr =/= downSendStateNext ){
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downSendCnt := 1.U
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} .elsewhen( downStreamCdrOut.io.axis.fire ){
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downSendCnt := downSendCnt + 1.U
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}
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downStreamCdrOut.io.axis.valid :=
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downSendStateCurr === DownSendStateNHead | downSendStateCurr === DownSendStateFData
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downStreamCdrOut.io.axis.bits.tdata := Mux1H(Seq(
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( downSendStateCurr === DownSendStateNHead ) -> downNewHeadShift.asUInt(63,56),
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( downSendStateCurr === DownSendStateFData ) -> downForwardFifo.io.deq.bits.tdata,
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))
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val downOldHead: Header_Info_Bundle
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val downLocalDataByte: UInt
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when( isDownNewHeadCreated ){
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downNewHeadShift.length := Mux( downOldHead.length >= downLocalDataByte, downOldHead.length - downLocalDataByte, 0.U )
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downNewHeadShift.operator := downOldHead.operator
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downNewHeadShift.param := downOldHead.param
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} .elsewhen( downStreamCdrOut.io.axis.fire & downSendStateCurr === DownSendStateNHead ){
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downNewHeadShift := (downNewHeadShift.asUInt << 8).asTypeOf(new Header_Info_Bundle)
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}
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downStreamCdrOut.io.axis.bits.tlast := ( downSendStateCurr === DownSendStateFData ) & downForwardFifo.io.deq.bits.tlast
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downStreamCdrOut.io.axis.bits.tuser :=
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(( downSendStateCurr === DownSendStateFData ) & downForwardFifo.io.deq.bits.tuser ) |
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isDownStreamError
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downForwardFifo.io.deq.ready :=
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downSendStateCurr === DownSendStateFData & downStreamCdrOut.io.axis.ready
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assert( ~(downStreamCdrIn.io.axis.valid & ~downStreamCdrIn.io.axis.ready) )
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}
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abstract class ShinSlvPhyDownStream extends ShinSlvPhyBase
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with ShinSlvPhyDownStreamRecv
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with ShinSlvPhyDownStreamSend{
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}
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trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
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val UpRecvStateIdle = 0.U
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val UpRecvStateOHead = 1.U
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val UpRecvStateFData = 2.U
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val UpRecvStateCRC = 3.U
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val upOldHead = Reg( new Header_Info_Bundle )
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val upNewHead = Reg( new Header_Info_Bundle )
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val upPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance)
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upStreamCdrIn.io.axis <> upPendBuf.io.enq
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val upRecvStateNext = Wire( UInt(3.W) )
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val upRecvStateCurr = RegNext( upRecvStateNext, 0.U )
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val upRecvCnt = Reg(UInt(10.W))
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val isLastDevice: Bool
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upRecvStateNext := Mux1H(Seq(
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(upRecvStateCurr === UpRecvStateIdle ) -> Mux( upPendBuf.io.deq.valid, UpRecvStateOHead, UpRecvStateIdle ),
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(upRecvStateCurr === UpRecvStateOHead) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( upRecvCnt === ((headByte)).U, UpRecvStateFData, UpRecvStateOHead), UpRecvStateIdle), UpRecvStateOHead ),
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(upRecvStateCurr === UpRecvStateFData) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( upRecvCnt === (upOldHead.length), UpRecvStateCRC, UpRecvStateFData), UpRecvStateIdle), UpRecvStateFData ),
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(upRecvStateCurr === UpRecvStateCRC ) -> Mux( upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast, UpRecvStateIdle, UpRecvStateCRC ),
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))
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when( upRecvStateCurr =/= upRecvStateNext){
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upRecvCnt := 1.U
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} .elsewhen( upPendBuf.io.deq.fire ){
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upRecvCnt := upRecvCnt + 1.U
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}
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val isLastDownStreamEnd = ( isLastDevice & (downRecvStateCurr === DownRecvStateCRC & downRecvStateNext === DownRecvStateIdle))
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//---------------
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when( (upRecvStateCurr === UpRecvStateOHead & upPendBuf.io.deq.fire) ){
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// upOldHead := Cat( upOldHead.asUInt.tail(8), upPendBuf.io.deq.bits.tdata ).asTypeOf(new Header_Info_Bundle)
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when( upRecvCnt === 1.U ) {
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upOldHead.length := upPendBuf.io.deq.bits.tdata
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} .elsewhen( upRecvCnt === 2.U ) {
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upOldHead.length := Cat( upOldHead.length, upPendBuf.io.deq.bits.tdata(7,4) )
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upOldHead.operator := upPendBuf.io.deq.bits.tdata(3,0)
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} .elsewhen( upRecvCnt === 3.U ){
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upOldHead.param(0) := upPendBuf.io.deq.bits.tdata
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} .elsewhen( upRecvCnt === 4.U ){
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upOldHead.param(0) := Cat( upOldHead.param(0), upPendBuf.io.deq.bits.tdata )
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} .elsewhen( upRecvCnt === 5.U ){
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upOldHead.param(1) := upPendBuf.io.deq.bits.tdata
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} .elsewhen( upRecvCnt === 6.U ){
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upOldHead.param(1) := Cat( upOldHead.param(1), upPendBuf.io.deq.bits.tdata )
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} .elsewhen( upRecvCnt === 7.U ){
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upOldHead.param(2) := upPendBuf.io.deq.bits.tdata
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} .elsewhen( upRecvCnt === 8.U ){
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upOldHead.param(2) := Cat( upOldHead.param(2), upPendBuf.io.deq.bits.tdata )
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}
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} .elsewhen( isLastDownStreamEnd ){
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upOldHead.operator := downOldHead.operator
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upOldHead.length := 0.U
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upOldHead.param := downOldHead.param
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}
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//---------------
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val upLocalDataByte = Mux1H(Seq(
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(upOldHead.operator === 0.U) -> OpInitByte.U,
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(upOldHead.operator === 1.U) -> OpBoardCastByte.U,
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(upOldHead.operator === 2.U) -> OpUniCastByte.U,
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))
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val isUpNewHeadCreated =
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RegNext(upRecvStateCurr === UpRecvStateOHead & upRecvStateNext === UpRecvStateFData, false.B) | //补一拍
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RegNext(isLastDownStreamEnd, false.B)
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when( isUpNewHeadCreated ){
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upNewHead.length := upOldHead.length + upLocalDataByte
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upNewHead.operator := upOldHead.operator
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upNewHead.param := upOldHead.param
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}
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val upForwardDataByte = upOldHead.length
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//---------------
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upForwardFifo.io.enq.valid :=
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upRecvStateCurr === UpRecvStateFData & upPendBuf.io.deq.fire
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upForwardFifo.io.enq.bits.tdata := upPendBuf.io.deq.bits.tdata
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upForwardFifo.io.enq.bits.tuser := upPendBuf.io.deq.bits.tuser
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upForwardFifo.io.enq.bits.tlast := upRecvCnt === (upForwardDataByte) | upPendBuf.io.deq.bits.tlast
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upPendBuf.io.deq.ready :=
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(upRecvStateCurr === UpRecvStateOHead) |
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(upRecvStateCurr === UpRecvStateFData) |
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(upRecvStateCurr === UpRecvStateCRC )
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val isUpStreamError = RegInit( false.B )
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when( (upRecvStateCurr === UpRecvStateIdle & upRecvStateNext === UpRecvStateOHead) | isLastDownStreamEnd ){
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isUpStreamError := false.B
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} .elsewhen( upForwardFifo.io.enq.fire & upForwardFifo.io.enq.bits.tuser ){
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isUpStreamError := true.B
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printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
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} .elsewhen( upRecvStateCurr === UpRecvStateOHead & upRecvStateNext === UpRecvStateIdle ){
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isUpStreamError := true.B
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printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
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} .elsewhen( upRecvStateCurr === UpRecvStateFData & upRecvStateNext === UpRecvStateIdle ){
|
||||
isUpStreamError := true.B
|
||||
printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
|
||||
} .elsewhen( upRecvStateCurr === UpRecvStateCRC & upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & upRecvCnt =/= 4.U ){
|
||||
isUpStreamError := true.B
|
||||
printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
|
||||
}
|
||||
|
||||
|
||||
|
||||
assert( ~(upRecvStateCurr === UpRecvStateFData & ~upForwardFifo.io.enq.ready), "Assert Failed, upStream Forward Fifo is OverFlow!" )
|
||||
|
||||
|
||||
}
|
||||
|
||||
trait ShinSlvPhyUpStreamSend{ this: ShinSlvPhyDownStream =>
|
||||
|
||||
|
||||
val UpSendStateIdle = 0.U
|
||||
val UpSendStateNHead = 1.U
|
||||
val UpSendStateLData = 2.U
|
||||
val UpSendStateFData = 3.U
|
||||
|
||||
|
||||
|
||||
val upSendStateNext = Wire( UInt(3.W) )
|
||||
val upSendStateCurr = RegNext( upSendStateNext, 0.U )
|
||||
|
||||
val upSendCnt = Reg(UInt(10.W))
|
||||
|
||||
val isUpNewHeadCreated: Bool
|
||||
val upLocalDataByte: UInt
|
||||
val isLastDevice: Bool
|
||||
val upForwardDataByte: UInt
|
||||
val upNewHead: Header_Info_Bundle
|
||||
val isUpStreamError: Bool
|
||||
|
||||
upSendStateNext := Mux1H(Seq(
|
||||
( upSendStateCurr === UpSendStateIdle ) -> Mux( isUpNewHeadCreated, UpSendStateNHead, UpSendStateIdle ),
|
||||
( upSendStateCurr === UpSendStateNHead ) -> Mux( upSendCnt === ((headByte)).U & upStreamCdrOut.io.axis.fire, UpSendStateLData, UpSendStateNHead),
|
||||
( upSendStateCurr === UpSendStateLData ) -> Mux( upSendCnt === (upLocalDataByte) & upStreamCdrOut.io.axis.fire, Mux( isLastDevice, UpSendStateIdle, UpSendStateFData), UpSendStateLData),
|
||||
( upSendStateCurr === UpSendStateFData ) -> Mux( upSendCnt === (upForwardDataByte) & upStreamCdrOut.io.axis.fire, UpSendStateIdle, UpSendStateFData),
|
||||
))
|
||||
|
||||
when( upSendStateCurr =/= upSendStateNext ){
|
||||
upSendCnt := 1.U
|
||||
} .elsewhen( upStreamCdrOut.io.axis.fire ){
|
||||
upSendCnt := upSendCnt + 1.U
|
||||
}
|
||||
|
||||
|
||||
val upNewHeadShift = Reg(new Header_Info_Bundle)
|
||||
|
||||
upStreamCdrOut.io.axis.valid :=
|
||||
upSendStateCurr === UpSendStateNHead | upSendStateCurr === UpSendStateLData | upSendStateCurr === UpSendStateFData
|
||||
|
||||
upStreamCdrOut.io.axis.bits.tdata := Mux1H(Seq(
|
||||
( upSendStateCurr === UpSendStateNHead ) -> upNewHeadShift.asUInt(63,56),
|
||||
( upSendStateCurr === UpSendStateLData ) -> upReg(upSendCnt-1.U),
|
||||
( upSendStateCurr === UpSendStateFData ) -> upForwardFifo.io.deq.bits.tdata,
|
||||
))
|
||||
|
||||
val upOldHead: Header_Info_Bundle
|
||||
when( isUpNewHeadCreated ){
|
||||
upNewHeadShift.length := upOldHead.length + upLocalDataByte
|
||||
upNewHeadShift.operator := upOldHead.operator
|
||||
upNewHeadShift.param := upOldHead.param
|
||||
} .elsewhen( upStreamCdrOut.io.axis.fire & upSendStateCurr === UpSendStateNHead ){
|
||||
upNewHeadShift := (upNewHeadShift.asUInt << 8).asTypeOf(new Header_Info_Bundle)
|
||||
}
|
||||
|
||||
|
||||
|
||||
upStreamCdrOut.io.axis.bits.tlast := ( upSendStateCurr === UpSendStateFData ) & upForwardFifo.io.deq.bits.tlast
|
||||
|
||||
upStreamCdrOut.io.axis.bits.tuser :=
|
||||
(( upSendStateCurr === UpSendStateFData ) & upForwardFifo.io.deq.bits.tuser ) |
|
||||
isUpStreamError
|
||||
|
||||
upForwardFifo.io.deq.ready :=
|
||||
upSendStateCurr === UpSendStateFData & upStreamCdrOut.io.axis.ready
|
||||
|
||||
assert( ~(upStreamCdrIn.io.axis.valid & ~upStreamCdrIn.io.axis.ready) )
|
||||
assert( ~(upSendStateCurr === UpSendStateFData & ~upForwardFifo.io.deq.valid) )
|
||||
|
||||
val isUpStreamEnd = (upSendStateCurr =/= UpSendStateIdle) & (upSendStateNext === UpSendStateIdle)
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
// trait ShinSlvPhyCloseLoop{ this: ShinSlvPhyDownStream =>
|
||||
// val isLastDevice: Bool
|
||||
|
||||
|
||||
// }
|
||||
|
||||
|
||||
abstract class ShinSlvLinkBase extends ShinSlvPhyDownStream
|
||||
with ShinSlvPhyUpStreamRecv
|
||||
with ShinSlvPhyUpStreamSend
|
||||
// with ShinSlvPhyCloseLoop
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
trait ShinSlvLinkInit{ this: ShinSlvLinkBase =>
|
||||
//定义初始化任务
|
||||
//下行定长包，各从机计算所在位置，更新ip地址寄存器，最后一个暂时通过IO实现闭环
|
||||
//以下行包头解析时间，从机位置号，标定数据计算更新RTC时间寄存器
|
||||
//上行根据包长，从站确定尾部伙伴数量（备用），
|
||||
//以上行包头解析时间放置本地时间
|
||||
//更新末尾寄存器
|
||||
|
||||
//热拔出 可以通过 io自动闭环，通过返回包缩短识别
|
||||
//热插入 必须带回寄存器信息，重新初始化，多发尾数据将被抛弃
|
||||
|
||||
//初始化应该下发 64*8 byte数据 对应 length = 512为slv0 504为slv1 ...
|
||||
|
||||
|
||||
val isInit = RegInit(false.B)
|
||||
val isLastInit = RegInit(false.B)
|
||||
val slvID = Reg(UInt(7.W))
|
||||
val slvNum = Reg(UInt(7.W))
|
||||
val slvRTC = Reg(UInt(64.W))
|
||||
|
||||
isLastDevice := isLastInit | io.isLast
|
||||
|
||||
val isLegalInitDownHead =
|
||||
downOldHead.operator === 0.U &
|
||||
downOldHead.length(2,0) === "b000".U
|
||||
|
||||
val isDownUpdate = RegInit(false.B)
|
||||
val isUpUpdate = RegInit(false.B)
|
||||
|
||||
val isLastDownStreamEnd: Bool
|
||||
val isUpStreamEnd: Bool
|
||||
val upOldHead: Header_Info_Bundle
|
||||
val isUpNewHeadCreated: Bool
|
||||
|
||||
|
||||
when( (isDownNewHeadCreated | isLastDownStreamEnd) & isLegalInitDownHead ){
|
||||
slvID := 64.U - (downOldHead.length >> 3)
|
||||
isDownUpdate := true.B
|
||||
} .elsewhen( isUpStreamEnd ){
|
||||
isDownUpdate := false.B
|
||||
}
|
||||
|
||||
when( isUpStreamEnd ){
|
||||
slvRTC := upOldHead.length >> 3 //Need Calibration
|
||||
} .otherwise{
|
||||
slvRTC := slvRTC + 1.U
|
||||
}
|
||||
|
||||
when( isLastDownStreamEnd & isLegalInitDownHead ){
|
||||
isLastInit := true.B
|
||||
} .elsewhen( isDownNewHeadCreated & isLegalInitDownHead ){
|
||||
isLastInit := false.B
|
||||
}
|
||||
|
||||
val isLegalInitUpHead =
|
||||
upOldHead.operator === 0.U &
|
||||
upOldHead.length(2,0) === "b000".U
|
||||
|
||||
when( isUpNewHeadCreated ){
|
||||
when( isLastDownStreamEnd ){
|
||||
slvNum := 65.U - (downOldHead.length >> 3)
|
||||
isUpUpdate := true.B
|
||||
} .elsewhen(isLegalInitUpHead){
|
||||
slvNum := (slvID + (upOldHead.length >> 3)) + 1.U
|
||||
isUpUpdate := true.B
|
||||
}
|
||||
} .elsewhen( isUpStreamEnd ){
|
||||
isUpUpdate := false.B
|
||||
}
|
||||
|
||||
when( isUpStreamEnd ){
|
||||
isInit := ~isDownStreamError & ~isUpStreamError & isDownUpdate & isUpUpdate
|
||||
}
|
||||
|
||||
val upRegMuxInit = isLegalInitUpHead
|
||||
when( upRegMuxInit ){
|
||||
upReg(0) := slvRTC(7,0)
|
||||
upReg(1) := slvRTC(15,8)
|
||||
upReg(2) := slvRTC(23,16)
|
||||
upReg(3) := slvRTC(31,24)
|
||||
upReg(4) := slvRTC(39,32)
|
||||
upReg(5) := slvRTC(47,40)
|
||||
upReg(6) := slvRTC(55,48)
|
||||
upReg(7) := slvRTC(63,56)
|
||||
}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
trait ShinSlvLinkBCast{ this: ShinSlvLinkBase =>
|
||||
|
||||
}
|
||||
|
||||
trait ShinSlvLinkUCast{ this: ShinSlvLinkBase =>
|
||||
|
||||
}
|
||||
|
||||
class ShinSlvBase extends ShinSlvLinkBase
|
||||
with ShinSlvLinkInit
|
||||
with ShinSlvLinkBCast
|
||||
with ShinSlvLinkUCast{
|
||||
assert( VecInit(upRegMuxInit).count((x:Bool) => (x === true.B)) <= 1.U, "Assert Failed, upReg Collision Used!\n" )
|
||||
|
||||
|
||||
val led = IO(UInt(8.W))
|
||||
led := RegEnable( 1.U << slvID, 0.U, ~RegNext(isInit) & isInit)
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user