展开文件结构
This commit is contained in:
Ruige Lee
328
src/main/scala/backBoard/shin/ShinMst.scala.bk
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328
src/main/scala/backBoard/shin/ShinMst.scala.bk
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package BACK
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import chisel3._
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import chisel3.util._
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class Header_Info_Bundle extends Bundle{
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val length = UInt(12.W) // nlength * 8bits
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val operator = UInt(4.W)
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val param = Vec(3, UInt(16.W))
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def init = operator === 0.U
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def sync = operator === 1.U
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def boardCast = operator === 2.U
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def uniCast = operator === 3.U
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}
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// class FSMC_Port_Bundle extends Bundle{
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// val ADIn = Input(UInt(16.W))
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// val ADOut = Output(UInt(16.W))
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// val ADOEn = Output(Bool())
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// val csn = Input(Bool())
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// val rdn = Input(Bool())
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// val wrn = Input(Bool())
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// val advn = Input(Bool())
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// }
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class ShinMstIO_Bundle extends Bundle{
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val FSMC = new FSMC_Port_Bundle
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val interrupt = Output(Bool())
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val testIO = Input(Bool())
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val serOut = Output(Bool())
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val serIn = Input(Bool())
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val overCLK = Input(Bool())
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}
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abstract class ShinMstPhyBase extends Module{
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val io: ShinMstIO_Bundle = IO(new ShinMstIO_Bundle)
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val mirrorDown = Module(new MirrorSRAMDP())
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val mirrorUp = Module(new MirrorSRAMDP())
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val mirrorReg = Module(new MirrorSRAMDP())
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val cdrOut = Module(new CDROut with chisel3.util.experimental.InlineInstance)
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val cdrIn = Module(new CDRIn with chisel3.util.experimental.InlineInstance)
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io.serOut := cdrOut.io.serDat
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cdrIn.io.serDat := io.serIn
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cdrIn.io.overCLK := io.overCLK
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mirrorDown.io.clockA := clock.asBool
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mirrorDown.io.clockB := clock.asBool
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mirrorUp.io.clockA := clock.asBool
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mirrorUp.io.clockB := clock.asBool
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mirrorReg.io.clockA := clock.asBool
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mirrorReg.io.clockB := clock.asBool
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mirrorReg.io.addrB := DontCare
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mirrorReg.io.datawB := DontCare
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mirrorReg.io.enwB := false.B
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mirrorReg.io.enrB := false.B
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}
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trait ShinMstSend{ this: ShinMstPhyBase =>
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val headByte = (new Header_Info_Bundle).getWidth/8
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require( headByte == 8 )
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val testIOShift = ShiftRegisters(io.testIO, headByte/2 + 1, false.B, true.B)
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val cdrPendBuf = Module( new Queue( new AXIS_Bundle(8), 1, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance) //Timing Opt
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cdrOut.io.axis <> cdrPendBuf.io.deq
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val sendHeader = Wire( new Header_Info_Bundle )
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sendHeader.length := 512.U
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sendHeader.operator := 0.U
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sendHeader.param(0) := 0.U
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sendHeader.param(1) := 0.U
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sendHeader.param(2) := 0.U
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val sendHead = sendHeader.asUInt
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/*
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val sendHeader = Reg( new Header_Info_Bundle )
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val sendHead = sendHeader.asUInt
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when( ~testIOShift(0) & io.testIO ){
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mirrorReg.io.addrB := 0.U
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mirrorReg.io.enrB := true.B
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} .elsewhen( ~testIOShift(1) & testIOShift(0) ){
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mirrorReg.io.addrB := 1.U
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mirrorReg.io.enrB := true.B
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sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle)
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} .elsewhen( ~testIOShift(2) & testIOShift(1) ){
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mirrorReg.io.addrB := 2.U
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mirrorReg.io.enrB := true.B
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sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle)
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} .elsewhen( ~testIOShift(3) & testIOShift(2) ){
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mirrorReg.io.addrB := 3.U
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mirrorReg.io.enrB := true.B
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sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle)
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} .elsewhen( ~testIOShift(4) & testIOShift(3) ){
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sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeOf(new Header_Info_Bundle)
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}
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*/
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val isSendTrig: Bool = ~testIOShift(4) & testIOShift(3)
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val isRecvEnd = Wire(Bool())
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val isTimeout = Wire(Bool())
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val sendStateNext = Wire( UInt(3.W) )
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val sendStateCurr = RegNext( sendStateNext, 0.U )
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val sendCntNext = Wire( UInt(10.W) )
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val sendCntCurr = RegNext(sendCntNext)
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sendStateNext := Mux1H(Seq(
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(sendStateCurr === 0.U) -> Mux( isSendTrig, 1.U, 0.U ),
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(sendStateCurr === 1.U) -> Mux( cdrPendBuf.io.enq.fire & sendCntCurr === (headByte-1).U, 2.U, 1.U ),
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(sendStateCurr === 2.U) -> Mux( cdrPendBuf.io.enq.fire & sendCntCurr === (sendHeader.length ) - 1.U, 3.U, 2.U ),
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(sendStateCurr === 3.U) -> Mux( isRecvEnd | isTimeout, 0.U, 3.U ),
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))
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sendCntNext := Mux1H(Seq(
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(sendStateCurr === 0.U) -> 0.U,
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(sendStateCurr === 1.U) -> Mux(cdrPendBuf.io.enq.fire, Mux( sendStateNext =/= 2.U, sendCntCurr + 1.U, 0.U ), sendCntCurr),
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(sendStateCurr === 2.U) -> Mux(cdrPendBuf.io.enq.fire, Mux( sendStateNext =/= 3.U, sendCntCurr + 1.U, 0.U ), sendCntCurr),
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))
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cdrPendBuf.io.enq.valid := sendStateCurr === 1.U | sendStateCurr === 2.U
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cdrPendBuf.io.enq.bits.tdata :=
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Mux1H(Seq(
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( sendStateCurr === 1.U ) -> (sendHead << (sendCntCurr << 3)).apply(63,56),
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( sendStateCurr === 2.U ) -> Mux( sendCntCurr.extract(0), mirrorDown.io.datarB(7,0), mirrorDown.io.datarB(15,8) ),
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))
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cdrPendBuf.io.enq.bits.tlast := sendStateCurr === 2.U & sendCntCurr === (sendHeader.length - 1.U )
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cdrPendBuf.io.enq.bits.tuser := false.B
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mirrorDown.io.enwB := false.B
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mirrorDown.io.datawB := 0.U
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mirrorDown.io.enrB := sendStateNext === 2.U
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mirrorDown.io.addrB := sendCntNext >> 1
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}
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trait ShinMstRecv{ this: ShinMstPhyBase =>
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val headByte: Int
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def isSendTrig: Bool
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val RecvStateIdle = 0.U
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val RecvStateArm = 1.U
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val RecvStateHead = 2.U
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val RecvStatePayLoad = 3.U
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val RecvStateCRC = 4.U
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val RecvStateDeArm = 5.U
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val recvStateNext = Wire( UInt(3.W) )
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val recvStateCurr = RegNext( recvStateNext, 0.U )
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val upPendBuf= Module( new Queue( new AXIS_Bundle(8), 2, pipe = true, flow = false ) with chisel3.util.experimental.InlineInstance )
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cdrIn.io.axis <> upPendBuf.io.enq
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val recvHeader = Reg( UInt( (new Header_Info_Bundle).getWidth.W) )
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val recvCnt = Reg(UInt(10.W))
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val recvLength = RegEnable(recvHeader(15,4), upPendBuf.io.deq.fire & ( recvStateCurr === RecvStateHead ) & recvCnt === 3.U)
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val isRecvEnd: Bool
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isRecvEnd := recvStateCurr === RecvStateDeArm
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io.interrupt := recvStateCurr === RecvStateDeArm
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recvStateNext := Mux1H(Seq(
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(recvStateCurr === RecvStateIdle) -> Mux( isSendTrig, RecvStateArm, RecvStateIdle ), //IDLE
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(recvStateCurr === RecvStateArm) -> Mux( upPendBuf.io.deq.valid, RecvStateHead, RecvStateArm ), //Arm
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(recvStateCurr === RecvStateHead) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (headByte).U, RecvStatePayLoad, RecvStateHead ), RecvStateDeArm ), RecvStateHead ), //Header
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(recvStateCurr === RecvStatePayLoad) -> Mux( upPendBuf.io.deq.fire, Mux( ~upPendBuf.io.deq.bits.tlast, Mux( recvCnt === (recvLength), RecvStateCRC, RecvStatePayLoad ), RecvStateDeArm ), RecvStatePayLoad ), //payload
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(recvStateCurr === RecvStateCRC) -> Mux( upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast, RecvStateDeArm, RecvStateCRC ),//crc
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(recvStateCurr === RecvStateDeArm) -> RecvStateIdle,//de-arm
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))
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when( recvStateCurr =/= recvStateNext ){
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recvCnt := 1.U
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} .elsewhen( upPendBuf.io.deq.fire ){
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recvCnt := recvCnt + 1.U
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}
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when( upPendBuf.io.deq.fire & ( recvStateCurr === RecvStateHead )) {
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recvHeader := Cat( recvHeader.tail(8), upPendBuf.io.deq.bits.tdata )
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}
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upPendBuf.io.deq.ready :=
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recvStateCurr === RecvStateHead | recvStateCurr === RecvStatePayLoad | recvStateCurr === RecvStateCRC
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val isRecvError = RegInit(false.B)
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when( recvStateCurr === RecvStateIdle & recvStateNext === RecvStateArm ){
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isRecvError := false.B
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} .elsewhen( upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tuser ){
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isRecvError := true.B
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printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n")
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} .elsewhen( recvStateCurr === RecvStateHead & recvStateNext === RecvStateDeArm ){
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isRecvError := true.B
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printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n")
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} .elsewhen( recvStateCurr === RecvStatePayLoad & recvStateNext === RecvStateDeArm ){
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isRecvError := true.B
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printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n")
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} .elsewhen( recvStateCurr === RecvStateCRC & upPendBuf.io.deq.fire & upPendBuf.io.deq.bits.tlast & recvCnt =/= 4.U ){
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isRecvError := true.B
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printf("Warning, Wrong Package Received in ShinMst, That could not happened!\n")
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}
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val recvDataLatch = RegEnable( upPendBuf.io.deq.bits.tdata, upPendBuf.io.deq.fire & recvStateCurr === 3.U & recvCnt.extract(0) )
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mirrorUp.io.enrB := false.B
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mirrorUp.io.enwB := upPendBuf.io.deq.fire & recvStateCurr === 3.U & ~recvCnt.extract(0)
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mirrorUp.io.datawB := Cat( upPendBuf.io.deq.bits.tdata, recvDataLatch )
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mirrorUp.io.addrB := recvCnt >> 1
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val recvRamAddr = Reg(UInt(8.W))
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when( recvStateCurr === 2.U ){
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recvRamAddr := 0.U
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} .elsewhen( recvStateCurr === 3.U & recvRamAddr =/= 4.U ){
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recvRamAddr := recvRamAddr + 1.U
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}
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mirrorReg.io.datawB := Mux1H(Seq(
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(recvStateCurr === 3.U & recvRamAddr === 0.U) -> (recvHeader >> 16*3),
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(recvStateCurr === 3.U & recvRamAddr === 1.U) -> (recvHeader >> 16*2),
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(recvStateCurr === 3.U & recvRamAddr === 2.U) -> (recvHeader >> 16*1),
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(recvStateCurr === 3.U & recvRamAddr === 3.U) -> (recvHeader >> 16*0),
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))
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when( recvStateCurr === 3.U & recvRamAddr =/= 4.U ){
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mirrorReg.io.addrB := recvRamAddr
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mirrorReg.io.enwB := true.B
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}
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val isTimeout: Bool
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isTimeout :=
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Counter( Range(0, 20000000), enable = recvStateCurr === 1.U | recvStateCurr === 2.U | recvStateCurr === 3.U, reset = recvStateCurr === 0.U | recvStateCurr === 5.U )._2
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}
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abstract class ShinMstLinkBase extends ShinMstPhyBase
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with ShinMstSend
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with ShinMstRecv
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trait ShinMstInterface{ this: ShinMstLinkBase =>
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io.FSMC.ADOEn := ~io.FSMC.rdn & ~io.FSMC.csn & io.FSMC.advn
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val latchAddr = RegEnable( io.FSMC.ADIn, ~io.FSMC.advn & ~io.FSMC.csn)
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val isAccessSRAM = ~latchAddr.extract(11)
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val isAccessReg = latchAddr.extract(11)
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val isAccessDown = ~latchAddr.extract(10)
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val activeAddr = latchAddr(9,0)
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mirrorDown.io.addrA := activeAddr
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mirrorDown.io.datawA := io.FSMC.ADIn
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mirrorDown.io.enwA := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn & isAccessDown
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mirrorDown.io.enrA := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn & isAccessDown
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mirrorUp.io.addrA := activeAddr
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mirrorUp.io.datawA := io.FSMC.ADIn
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mirrorUp.io.enwA := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn & ~isAccessDown
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mirrorUp.io.enrA := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn & ~isAccessDown
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mirrorReg.io.addrA := activeAddr
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mirrorReg.io.datawA := io.FSMC.ADIn
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mirrorReg.io.enwA := isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn
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mirrorReg.io.enrA := isAccessReg & ~io.FSMC.csn & ~io.FSMC.rdn
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io.FSMC.ADOut := Mux( isAccessReg, mirrorReg.io.datarA, Mux( isAccessDown, mirrorDown.io.datarA, mirrorUp.io.datarA) )
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}
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class ShinMst extends ShinMstLinkBase
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with ShinMstInterface
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