ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

:Merge branch 'feature_shintop' into eb_dev

Browse Source
This commit is contained in:
bacon
2025-07-30 23:14:37 +08:00
parent 9cf5346b3d 8ba8ff0e9e
commit 656986a8ab
6 changed files with 151 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/main/scala/backBoard/ebus/CDRIn.scala
View File

@@ -10,7 +10,6 @@ class CDRInIO extends Bundle{
val serDat = Input(Bool())
val overCLK = Input(Bool())
val initEncryptor = Flipped(Valid(UInt(128.W)))
}
@@ -19,9 +18,6 @@ abstract class CDRInBase extends Module{
val io: CDRInIO = IO(new CDRInIO)
val encryptor = Module(new Encryptor)
encryptor.io.init := io.initEncryptor
encryptor.io.op.ready := io.axis.fire
}
@@ -131,9 +127,9 @@ trait CDRInAxis{ this: CDRInBase =>
val payloadLen = RegInit(0.U(12.W))
when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
payloadLen := Cat( shiftData ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ), 0.U(4.W) )
payloadLen := Cat( shiftData, 0.U(4.W) )
} .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
payloadLen := Cat( payloadLen(11,4), shiftData(7,4) ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits(7,4), 0.U ) )
payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
}
stateNext :=
@@ -174,7 +170,7 @@ trait CDRInAxis{ this: CDRInBase =>
val axis_valid = RegInit(false.B)
val axis_tdata = RegEnable( shiftData ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ), bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
val axis_tuser = false.B
val axis_tlast = RegNext( stateCurr === STATE_PAYLOAD & stateNext === STATE_IDLE, false.B )

8
src/main/scala/backBoard/ebus/CDROut.scala
View File

@@ -14,7 +14,6 @@ class CDROutIO extends Bundle{
val axis = Flipped(Decoupled(new AXIS_Bundle(8)))
val serDat = Output(Bool())
val initEncryptor = Flipped(Valid(UInt(128.W)))
}
@@ -22,9 +21,6 @@ class CDROutIO extends Bundle{
class CDROut extends Module{
val io: CDROutIO = IO(new CDROutIO)
val encryptor = Module(new Encryptor)
encryptor.io.init := io.initEncryptor
encryptor.io.op.ready := io.axis.fire
def STATE_IDLE = 0.U
@@ -72,10 +68,10 @@ class CDROut extends Module{
when( stateCurr === STATE_PREAMBLE ){
shiftData := MuxCase( ETH_PRE, Array(
( byteCnt === 6.U ) -> ETH_SFD,
( byteCnt === 7.U ) -> Dualb4b5Encoder( io.axis.bits.tdata ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ) ),
( byteCnt === 7.U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
))
} .elsewhen( stateCurr === STATE_PAYLOAD ){
shiftData := Dualb4b5Encoder(io.axis.bits.tdata ^ Mux( encryptor.io.op.valid, encryptor.io.op.bits, 0.U ) )
shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
}
}
}