diff --git a/Makefile b/Makefile
index 125a340..61d13b0 100644
--- a/Makefile
+++ b/Makefile
@@ -53,6 +53,19 @@ testShin:
 	vvp  -N ./tb/build/shinTest.iverilog -lxt2 -fst || true
 	./tb/shinTest/check_testcase.py
 
+testShinClk:
+	./tb/shinTest/gen_pkt_clk.py
+	mkdir -p generated/log
+	rm -rf generated/log/*
+	iverilog -Wall  \
+	-o ./tb/build/shinTest_clk.iverilog  \
+	-y ./generated/shin \
+	-I ./generated/shin \
+	-D RANDOMIZE_REG_INIT \
+	./tb/shinTest/ShinTopSpiTb_clk.v 
+	vvp  -N ./tb/build/shinTest_clk.iverilog -lxt2 -fst || true
+	./tb/shinTest/check_testcase.py
+
 testCDR:
 	iverilog -Wall  \
 	-o ./tb/build/simCDR.iverilog  \
@@ -75,6 +88,9 @@ vcdFilter:
 vcdShin:
 	gtkwave ./tb/build/wave.vcd 1>/dev/null 2>&1 &
 
+vcdShinClk:
+	gtkwave ./tb/build/wave_clk.vcd 1>/dev/null 2>&1 &
+
 fstShin:
 	gtkwave ./tb/build/wave.fst 1>/dev/null 2>&1 &
 
diff --git a/tb/shinTest/ShinTopSpiTb_clk.v b/tb/shinTest/ShinTopSpiTb_clk.v
index 60ae9f2..3c64f9b 100644
--- a/tb/shinTest/ShinTopSpiTb_clk.v
+++ b/tb/shinTest/ShinTopSpiTb_clk.v
@@ -1,34 +1,7 @@
 `timescale 1 ns / 1 ps
 
 `define ENABLE_REG_RW1_TEST                 "generated/log/reg_rw1_tc.log"
-//`define ENABLE_ENCRYPTION
-//`define ENABLE_DET1_TEST                    "generated/log/det1_tc.log"
-//`define ENABLE_DET2_TEST                    "generated/log/det2_tc.log"
-//`define ENABLE_SET_ADDR_TEST                "generated/log/set_addr_tc.log"
-//`define ENABLE_INT_INIT_TEST                "generated/log/int_init_tc.log"
-//`define ENABLE_DET_ERR1_TEST                "generated/log/det_err1_tc.log"
-//`define ENABLE_SMx_SEND1_TEST               "generated/log/sm_send1_tc.log"
-//`define ENABLE_SMx_SEND2_TEST               "generated/log/sm_send2_tc.log"
-//`define ENABLE_SMx_SEND3_TEST               "generated/log/sm_send3_tc.log"
-//`define ENABLE_ERR_PKT1_TEST              "generated/log/err_pkt1_tc.log"
-//`define ENABLE_ERR_PKT2_TEST              "generated/log/err_pkt2_tc.log"
-//`define ENABLE_ERR_PKT3_TEST              "generated/log/err_pkt3_tc.log"
 
-//`define ENABLE_EXCHG_DATA_SEQ0_TEST       "generated/log/exchg_data_seq0_tc.log"
-//`define ENABLE_EXCHG_DATA_SEQ1_TEST       "generated/log/exchg_data_seq1_tc.log"
-//`define ENABLE_EXCHG_DATA_SEQ2_TEST       "generated/log/exchg_data_seq2_tc.log"
-//`define ENABLE_EXCHG_DATA_SEQ3_TEST       "generated/log/exchg_data_seq3_tc.log"
-
-//`define ENABLE_BC_R_TEST                  "generated/log/bc_r_tc.log"
-//`define ENABLE_BC_W_TEST                  "generated/log/bc_w_tc.log"
-//`define ENABLE_BC_RW_TEST                 "generated/log/bc_rw_tc.log"
-
-//`define ENABLE_SYNC_TEST                  "generated/log/sync_tc.log"
-//`define ENABLE_SYNC_SIG0_TEST             "generated/log/sync_sig0_tc.log"
-//`define ENABLE_SYNC_SIG1_TEST             "generated/log/sync_sig1_tc.log"
-//`define ENABLE_RESET_TEST                 "generated/log/reset_tc.log"
-
-//`define ENABLE_WD1_TEST                   "generated/log/wd1_tc.log"
 
 module ShinTopSpiTb(
 
@@ -473,7 +446,7 @@ initial
 begin
   	spidata_file = $fopen("spi_trans_data.txt", "w");
   	if (!spidata_file) $display("文件打开失败");
-	$dumpfile("./tb/build/wave.fst"); //生成的vcd文件名称
+	$dumpfile("./tb/build/wave_clk.fst"); //生成的vcd文件名称
 	$dumpvars(0, ShinTopSpiTb);//tb模块名称
 end
 
diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py
index 37ce06c..dc6ae45 100755
--- a/tb/shinTest/gen_pkt.py
+++ b/tb/shinTest/gen_pkt.py
@@ -47,9 +47,9 @@ if __name__ == '__main__':
     #add_tc_2_runlist(errorPkt.tc38())
 
 
-    add_tc_2_runlist(base.tc1())
-    add_tc_2_runlist(base.tc2())
-    add_tc_2_runlist(base.tc3())
+    #add_tc_2_runlist(base.tc1())
+    #add_tc_2_runlist(base.tc2())
+    #add_tc_2_runlist(base.tc3())
     #add_tc_2_runlist(base.tc4())
     #add_tc_2_runlist(base.tc5())
     #add_tc_2_runlist(base.tc6())