diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 7cee3a9..e332f12 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -768,7 +768,7 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
     )
 
     sReg.ebmmu(i).op :=
-      RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) )
+      RegEnable( io.lvds.dataw, false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) )
 
     sReg.ebmmu(i).isEnable :=
       RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) )
diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala
index 6d5b74e..5c39310 100644
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -625,7 +625,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
     } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
       addrr := acquireUpPhyAddrr
     }
-  } .elsewhen( isLvdsEnR ){
+  } .elsewhen( upRecParser.io.data.fire ){
     when( 
       ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD   | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR  ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) |
       ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR)
@@ -649,7 +649,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
     upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
     upRecFifo(0).io.enq.bits  := 
       Mux( 
-           ( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR   ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) | upSubMsgInfo(0).isLgcIndex), upStreamData,
+           ( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR   ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) | (upSubMsgInfo(0).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData,
         Mux( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits,
           upRecParser.io.data.bits )
       )
@@ -664,7 +664,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
     upRecFifo(1).io.enq.valid := upRecParser.io.data.valid
     upRecFifo(1).io.enq.bits  :=
       Mux( 
-           ( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR   ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) | upSubMsgInfo(1).isLgcIndex), upStreamData,
+           ( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR   ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) | (upSubMsgInfo(1).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData,
         Mux( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits,
           upRecParser.io.data.bits
         )