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完成编译，准备接入CPU查看信号逻辑

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This commit is contained in:
RuigeLee
2023-10-17 16:38:18 +08:00
parent 7c71c005f8
commit 629d9486d1
8 changed files with 118 additions and 191 deletions
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0
src/main/scala/mac/AsyncFifo.scala → src/main/scala/mac/AsyncFifo.scala.bk
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51
src/main/scala/mac/MAC.scala
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@@ -11,31 +11,6 @@ import freechips.rocketchip.interrupts._
class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
val tlMasterNode =
TLManagerNode(Seq(TLSlavePortParameters.v1(
managers = Seq(TLSlaveParameters.v1(
address = Seq(AddressSet(0x30000400L, 0x03FFL)),
regionType = RegionType.VOLATILE,
executable = false,
fifoId = Some(2),
supportsGet = TransferSizes(8/8, 32/8),
supportsPutFull = TransferSizes(8/8, 32/8),
supportsPutPartial = TransferSizes(8/8, 32/8)
)),
beatBytes = 32/8)))
val tlClientNode = TLClientNode(Seq(TLMasterPortParameters.v1(
Seq(TLMasterParameters.v1(
name = "tlMst",
sourceId = IdRange(0, 1),
))
)))
val ethReg = LazyModule(new MacReg)
@@ -76,12 +51,6 @@ class MacImp(outer: Mac)(implicit p: Parameters) extends LazyModuleImp(outer) wi
val io = IO(new MacIO)
val ( slv_bus, slv_edge ) = outer.tlMasterNode.in.head
val ( mst_bus, mst_edge ) = outer.tlClientNode.out.head
val r_ClkDiv = Wire(UInt(8.W))
val r_MiiNoPre = Wire(Bool())
@@ -679,25 +648,7 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
val wishbone = Module(new MacTileLink(slv_edge, mst_edge))
wishbone.io.tlSlv.A.valid := slv_bus.a.valid
wishbone.io.tlSlv.A.bits := slv_bus.a.bits
slv_bus.a.ready := wishbone.io.tlSlv.A.ready
slv_bus.d.valid := wishbone.io.tlSlv.D.valid
slv_bus.d.bits := wishbone.io.tlSlv.D.bits
wishbone.io.tlSlv.D.ready := slv_bus.d.ready
wishbone.io.tlMst.D.bits := mst_bus.d.bits
wishbone.io.tlMst.D.valid := mst_bus.d.valid
mst_bus.d.ready := wishbone.io.tlMst.D.ready
mst_bus.a.valid := wishbone.io.tlMst.A.valid
mst_bus.a.bits := wishbone.io.tlMst.A.bits
wishbone.io.tlMst.A.ready := mst_bus.a.ready
val wishbone = Module(new MacTileLink)
wishbone.io.RetryCntLatched := RetryCntLatched

173
src/main/scala/mac/MacTilelink.scala
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@@ -2,6 +2,7 @@ package MAC
import chisel3._
import chisel3.util._
import Switch._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.diplomacy._
@@ -14,54 +15,10 @@ import org.chipsalliance.cde.config._
abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Module{
class MacTileLinkSlaveIO extends Bundle{
val A = Flipped(Decoupled(new TLBundleA(edgeIn.bundle)))
val D = Decoupled(new TLBundleD(edgeIn.bundle))
}
class MacTileLinkMasterIO extends Bundle{
val A = Decoupled(new TLBundleA(edgeOut.bundle))
val D = Flipped(Decoupled(new TLBundleD(edgeOut.bundle)))
}
abstract class MacTileLinkBase() extends Module{
class MacTileLinkIO extends Bundle{
val tlSlv = new MacTileLinkSlaveIO
val tlMst = new MacTileLinkMasterIO
// Tx Status signals
val RetryCntLatched = Input(UInt(4.W)) // Latched Retry Counter
val RetryLimit = Input(Bool()) // Retry limit reached (Retry Max value +1 attempts were made)
val LateCollLatched = Input(Bool()) // Late collision occured
val DeferLatched = Input(Bool()) // Defer indication (Frame was defered before sucessfully sent)
val CarrierSenseLost = Input(Bool()) // Carrier Sense was lost during the frame transmission
// Tx
val PerPacketCrcEn = Output(Bool()) // Per packet crc enable
val PerPacketPad = Output(Bool()) // Per packet pading
//Register
val r_TxEn = Input(Bool()) // Transmit enable
val BlockingTxStatusWrite = Output(Bool())
val TxUsedData = Input(Bool()) // Transmit packet used data
val TxValidBytesLatched = Output(UInt(2.W))
val TxRetrySync = Input(Bool())
val TxAbortSync = Input(Bool()) // Transmit packet abort
val TxDoneSync = Input(Bool()) // Transmission ended
val r_RxEn = Input(Bool()) // Receive enable
val RxDataLatched2_rxclk = Input(UInt(32.W))
val WriteRxDataToFifoSync = Input(Bool())
@@ -70,8 +27,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
val RxStatusInLatched_rxclk = Input(UInt(9.W))
val ShiftEndedSync = Input(Bool())
val RxReady = Output(Bool())
val rxDeq = new RevBuff_Enq_Bundle
val TxStartFrm_wb = Output(Bool())
@@ -81,7 +36,26 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
val TxData_wb = Output(UInt(32.W))
val ReadTxDataFromFifo_sync = Input(Bool())
val txEnq = Flipped(new TxBuff_Deq_Bundle)
// Tx Status signals
val RetryCntLatched = Input(UInt(4.W)) // Latched Retry Counter
val RetryLimit = Input(Bool()) // Retry limit reached (Retry Max value +1 attempts were made)
val LateCollLatched = Input(Bool()) // Late collision occured
val DeferLatched = Input(Bool()) // Defer indication (Frame was defered before sucessfully sent)
val CarrierSenseLost = Input(Bool()) // Carrier Sense was lost during the frame transmission
val PerPacketCrcEn = Output(Bool()) // Per packet crc enable
val PerPacketPad = Output(Bool()) // Per packet pading
//Register
val r_TxEn = Input(Bool()) // Transmit enable
val BlockingTxStatusWrite = Output(Bool())
val TxUsedData = Input(Bool()) // Transmit packet used data
val TxValidBytesLatched = Output(UInt(2.W))
val TxRetrySync = Input(Bool())
val TxAbortSync = Input(Bool()) // Transmit packet abort
val TxDoneSync = Input(Bool()) // Transmission ended
}
@@ -90,6 +64,8 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
val io = IO(new MacTileLinkIO)
val txBuff = Module(new TxBuff)
val rxBuff = Module(new RxBuff)
val ShiftEndedSyncPluse = io.ShiftEndedSync & ~RegNext(io.ShiftEndedSync, false.B)
val RxAbortPluse = io.RxAbortSync & ~RegNext(io.RxAbortSync, false.B)
@@ -98,16 +74,16 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
val RxReady = RegInit(false.B); io.RxReady := RxReady
val rxDeqCtrlValid = RegInit(false.B)
io.rxDeq.ctrl.valid := rxDeqCtrlValid
io.rxDeq.ctrl.bits.LatchedRxLength := RegEnable(io.LatchedRxLength_rxclk, ShiftEndedSyncPluse | RxAbortPluse)
io.rxDeq.ctrl.bits.RxStatusInLatched := RegEnable(io.RxStatusInLatched_rxclk, ShiftEndedSyncPluse | RxAbortPluse)
io.rxDeq.ctrl.bits.isRxAbort := RegEnable(RxAbortPluse, false.B, ShiftEndedSyncPluse | RxAbortPluse)
val rxBuffCtrlValid = RegInit(false.B)
rxBuff.io.enq.ctrl.valid := rxBuffCtrlValid
rxBuff.io.enq.ctrl.bits.LatchedRxLength := RegEnable(io.LatchedRxLength_rxclk, ShiftEndedSyncPluse | RxAbortPluse)
rxBuff.io.enq.ctrl.bits.RxStatusInLatched := RegEnable(io.RxStatusInLatched_rxclk, ShiftEndedSyncPluse | RxAbortPluse)
rxBuff.io.enq.ctrl.bits.isRxAbort := RegEnable(RxAbortPluse, false.B, ShiftEndedSyncPluse | RxAbortPluse)
when( io.rxDeq.ctrl.fire ){
rxDeqCtrlValid := false.B
when( rxBuff.io.enq.ctrl.fire ){
rxBuffCtrlValid := false.B
} .elsewhen( ShiftEndedSyncPluse | RxAbortPluse ){
rxDeqCtrlValid := true.B
rxBuffCtrlValid := true.B
}
@@ -115,15 +91,15 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
// RxReady generation
when(ShiftEndedSyncPluse | RxAbortPluse ){
RxReady := false.B
} .elsewhen( io.r_RxEn & (io.rxDeq.data.ready) ){
} .elsewhen( io.r_RxEn & (rxBuff.io.enq.data.ready) ){
RxReady := true.B
}
io.rxDeq.data.bits := io.RxDataLatched2_rxclk
io.rxDeq.data.valid := WriteRxDataToFifoSyncPluse
rxBuff.io.enq.data.bits := io.RxDataLatched2_rxclk
rxBuff.io.enq.data.valid := WriteRxDataToFifoSyncPluse
assert( (~io.rxDeq.data.valid & ~io.rxDeq.data.ready), "Assert Failed, rx overrun!" )
assert( (~rxBuff.io.enq.data.valid & ~rxBuff.io.enq.data.ready), "Assert Failed, rx overrun!" )
@@ -151,17 +127,16 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
val TxLength = RegInit(0.U(16.W))
val LatchedTxLength = RegInit(0.U(16.W))
val TxRetryPulse = io.TxRetrySync & ~RegNext(io.TxRetrySync, false.B)
val TxDonePulse = io.TxDoneSync & ~RegNext(io.TxDoneSync, false.B)
val TxAbortPulse = io.TxAbortSync & ~RegNext(io.TxAbortSync, false.B)
val txRetryPulse = io.TxRetrySync & ~RegNext(io.TxRetrySync, false.B)
val txDonePulse = io.TxDoneSync & ~RegNext(io.TxDoneSync, false.B)
val txAbortPulse = io.TxAbortSync & ~RegNext(io.TxAbortSync, false.B)
val ReadTxDataFromFifoSyncPluse = io.ReadTxDataFromFifo_sync & ~RegNext(io.ReadTxDataFromFifo_sync, false.B)
val TxStatus = RegInit(0.U(4.W)) //[14:11]
io.PerPacketPad := TxStatus.extract(1)
io.PerPacketCrcEn := TxStatus.extract(0)
io.PerPacketPad := RegEnable(txBuff.io.deq.req.bits.PerPacketPad, false.B, txBuff.io.deq.req.fire)
io.PerPacketCrcEn := RegEnable(txBuff.io.deq.req.bits.PerPacketCrcEn, false.B, txBuff.io.deq.req.fire)
when( io.txEnq.req.fire ){
when( txBuff.io.deq.req.fire ){
TxStartFrm_wb := true.B
} .elsewhen(io.TxStartFrm_syncb){
TxStartFrm_wb := false.B
@@ -170,18 +145,15 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
when((TxLength === 0.U) & io.TxUsedData){
TxEndFrm_wb := true.B
} .elsewhen(TxRetryPulse | TxDonePulse | TxAbortPulse){
} .elsewhen(txRetryPulse | txDonePulse | txAbortPulse){
TxEndFrm_wb := false.B
}
when( io.txEnq.req.fire ){
TxStatus :=
Cat(
io.txEnq.req.bits.irq, io.txEnq.req.bits.wr, io.txEnq.req.bits.pad, io.txEnq.req.bits.crc
)
TxLength := io.txEnq.req.bits.txLength
LatchedTxLength := io.txEnq.req.bits.txLength
} .elsewhen( io.txEnq.data.fire ){
when( txBuff.io.deq.req.fire ){
TxLength := txBuff.io.deq.req.bits.txLength
LatchedTxLength := txBuff.io.deq.req.bits.txLength
} .elsewhen( txBuff.io.deq.data.fire ){
when( TxLength < 4.U ){
TxLength := 0.U
} .otherwise{
@@ -191,18 +163,21 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
val txRespValid = RegInit(false.B)
val txRespBits = Reg(new Transmit_Deq_Resp_Bundle)
io.txEnq.resp.valid := txRespValid
io.txEnq.resp.bits :=
RegEnable(
Cat(LatchedTxLength, 0.U(1.W), TxStatus, 0.U(2.W), false.B, io.RetryCntLatched, io.RetryLimit, io.LateCollLatched, io.DeferLatched, io.CarrierSenseLost),
TxRetryPulse | TxDonePulse | TxAbortPulse
)
txBuff.io.deq.resp.valid := txRespValid
txBuff.io.deq.resp.bits := txRespBits
when( io.txEnq.resp.fire ){
when( txBuff.io.deq.resp.fire ){
txRespValid := false.B
} .elsewhen( TxRetryPulse | TxDonePulse | TxAbortPulse ){
} .elsewhen( txRetryPulse | txDonePulse | txAbortPulse ){
txRespValid := true.B
txRespBits.RetryCntLatched := io.RetryCntLatched
txRespBits.RetryLimit := io.RetryLimit
txRespBits.LateCollLatched := io.LateCollLatched
txRespBits.DeferLatched := io.DeferLatched
txRespBits.CarrierSenseLost := io.CarrierSenseLost
txRespBits.isClear := txAbortPulse | txRetryPulse
}
@@ -210,9 +185,9 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
val isTxBusy = RegInit(false.B); io.txEnq.req.ready := ~isTxBusy & io.r_TxEn_q
val isTxBusy = RegInit(false.B); txBuff.io.deq.req.ready := ~isTxBusy & io.r_TxEn
when(io.txEnq.req.fire){
when(txBuff.io.deq.req.fire){
isTxBusy := true.B
} .elsewhen(txRetryPulse | txDonePulse | txAbortPulse){
isTxBusy := false.B
@@ -224,12 +199,11 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
io.txEnq.data.ready := ReadTxDataFromFifoSyncPluse & ~tx_fifo.io.empty
assert( ~(io.txEnq.data.ready & ~io.txEnq.data.valid), "Assert Failed, Tx should never under run!" )
txBuff.io.deq.data.ready := ReadTxDataFromFifoSyncPluse
assert( ~(txBuff.io.deq.data.ready & ~txBuff.io.deq.data.valid), "Assert Failed, Tx should never under run!" )
io.TxData_wb := io.txEnq.data.bits
io.TxData_wb := txBuff.io.deq.data.bits
tx_fifo.io.clear := txAbortPulse | txRetryPulse
@@ -265,7 +239,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
// Latching valid bytes
when(LatchValidBytesPluse){
TxValidBytesLatched := Mux(TxLength < 4.U, TxLength(1,0), 0.U)
} .elsewhen(TxRetryPulse | TxDonePulse | TxAbortPulse){
} .elsewhen(txRetryPulse | txDonePulse | txAbortPulse){
TxValidBytesLatched := 0.U
}
@@ -273,13 +247,17 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
}
class MacTileLink() extends MacTileLinkBase(){
txBuff.io.enq.ctrl.valid := false.B
txBuff.io.enq.data.valid := false.B
txBuff.io.enq.data.bits := 0.U
rxBuff.io.deq.data.ready := false.B
rxBuff.io.deq.ctrl.ready := false.B
}
@@ -287,13 +265,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
class MacTileLink(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends MacTileLinkBase(edgeIn, edgeOut)

41
src/main/scala/Switch/RevBuff.scala → src/main/scala/mac/RxBuff.scala
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@@ -1,33 +1,33 @@
package MAC
package Switch
import chisel3._
import chisel3.util._
class RevBuff_Enq_Ctrl_Bundle extends Bundle{
class Receive_Enq_Ctrl_Bundle extends Bundle{
val LatchedRxLength = UInt(16.W)
val RxStatusInLatched = UInt(9.W)
val isRxAbort = Bool()
}
class RevBuff_Deq_Ctrl_Bundle extends Bundle{
class Receive_Deq_Ctrl_Bundle extends Bundle{
}
class RevBuff_Enq_Bundle extends Bundle{
class Receive_Enq_Bundle extends Bundle{
val data = Decoupled(UInt(32.W))
val ctrl = Decoupled(new RevBuff_Enq_Ctrl_Bundle)
val ctrl = Decoupled(new Receive_Enq_Ctrl_Bundle)
}
class RevBuff_Deq_Bundle extends Bundle{
class Receive_Deq_Bundle extends Bundle{
val data = Decoupled(UInt(32.W))
val ctrl = Decoupled(new RevBuff_Deq_Ctrl_Bundle)
val ctrl = Decoupled(new Receive_Deq_Ctrl_Bundle)
}
class RevBuffIO extends Bundle{
val enq = Flipped(new RevBuff_Enq_Bundle)
val deq = new RevBuff_Deq_Bundle
class RxBuffIO extends Bundle{
val enq = Flipped(new Receive_Enq_Bundle)
val deq = new Receive_Deq_Bundle
}
@@ -38,14 +38,14 @@ class Packet_Info_Bundle extends Bundle{
}
class RevBuff extends Module{
val io: RevBuffIO = IO(new RevBuffIO)
class RxBuff extends Module{
val io: RxBuffIO = IO(new RxBuffIO)
val isPing = RegInit(true.B)
val isPong = ~isPing
val pipoBuff = for( i <- 0 until 2 ) yiled { Module(new Queue( UInt(32.W), 2048/4 )) }
val pipoInfo = for( i <- 0 until 2 ) yiled { Reg(new Packet_Info_Bundle) }
val pipoBuff = for( i <- 0 until 2 ) yield { Module(new Queue( UInt(32.W), 2048/4 )) }
val pipoInfo = for( i <- 0 until 2 ) yield { Reg(new Packet_Info_Bundle) }
val recCnt = RegInit(0.U(3.W))
@@ -53,9 +53,9 @@ class RevBuff extends Module{
pipoBuff(0).io.enq.bits := io.enq.data.bits
pipoBuff(1).io.enq.valid := isPong & io.enq.data.valid
pipoBuff(1).io.enq.btis := io.enq.data.bits
pipoBuff(1).io.enq.bits := io.enq.data.bits
io.enq.data.ready := (isPing & io.enq.data.ready) | (isPong & io.enq.data.ready)
io.enq.data.ready := (isPing & pipoBuff(0).io.enq.ready) | (isPong & pipoBuff(1).io.enq.ready)
io.enq.ctrl.ready := true.B
pipoBuff(0).reset := reset.asBool | (isPing & io.enq.ctrl.fire & io.enq.ctrl.bits.isRxAbort)
@@ -77,7 +77,7 @@ class RevBuff extends Module{
when( io.enq.ctrl.fire ){
recCnt := 0.U
} .elsewhen( io.enq.data.fire ){
when( recCnt < 5 ){
when( recCnt < 5.U ){
recCnt := recCnt + 1.U
when( isPing ){
pipoInfo(0).header(recCnt) := io.enq.data.bits
@@ -91,7 +91,14 @@ class RevBuff extends Module{
pipoBuff(0).io.deq.ready := false.B
pipoBuff(1).io.deq.ready := false.B
io.deq.data.valid := false.B
io.deq.data.bits := 0.U
io.deq.ctrl.valid := false.B
io.deq.ctrl.bits := 0.U.asTypeOf(new Receive_Deq_Ctrl_Bundle)
}

19
src/main/scala/Switch/TxBuff.scala → src/main/scala/mac/TxBuff.scala
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@@ -1,4 +1,4 @@
package MAC
package Switch
import chisel3._
import chisel3.util._
@@ -10,11 +10,19 @@ class Transmit_Enq_Ctrl_Bundle extends Bundle{
class Transmit_Deq_Req_Bundle extends Bundle{
val txLength = UInt(16.W)
val PerPacketCrcEn = Bool()
val PerPacketPad = Bool()
}
class Transmit_Deq_Resp_Bundle extends Bundle{
val RetryCntLatched = UInt(4.W)
val RetryLimit = Bool()
val LateCollLatched = Bool()
val DeferLatched = Bool()
val CarrierSenseLost = Bool()
val isClear = Bool()
}
class Transmit_Enq_Bundle extends Bundle{
@@ -39,8 +47,15 @@ class TxBuffIO extends Bundle{
class TxBuff extends Module{
val io: TxBuffIO = IO(new TxBuffIO)
io.enq.data.ready := true.B
io.enq.ctrl.ready := true.B
io.deq.data.valid := false.B
io.deq.data.bits := 0.U
io.deq.req.valid := false.B
io.deq.req.bits := 0.U.asTypeOf(new Transmit_Deq_Req_Bundle)
io.deq.resp.ready := true.B
}

4
src/main/scala/mac/WithMac.scala
View File

@@ -12,8 +12,8 @@ trait WithManyMacMix { this: BaseSubsystem =>
val mac0 = LazyModule(new Mac)
sbus.coupleFrom("mac_mst") { _ := TLBuffer() := mac0.tlClientNode }
pbus.coupleTo("mac_cfg") { mac0.tlMasterNode := TLFragmenter(pbus) := _ }
// sbus.coupleFrom("mac_mst") { _ := TLBuffer() := mac0.tlClientNode }
// pbus.coupleTo("mac_cfg") { mac0.tlMasterNode := TLFragmenter(pbus) := _ }
pbus.coupleTo("mac_cfg") { mac0.ethReg.configNode := TLFragmenter(pbus) := _ }
ibus.fromSync := mac0.ethReg.int_node

20
src/test/scala/gcd/Mac_test_top.scala
View File

@@ -14,21 +14,6 @@ class MacTest(implicit p: Parameters) extends Mac{
val tlRAM = TLRAM(
address = AddressSet(0x00000000L, 0x001FFFFFL),
cacheable = false,
executable = false,
atomics = false,
beatBytes = 4,
sramReg = true,
devName = None,
)
tlRAM := tlClientNode
val tlClientIONode =
TLClientNode(Seq(TLMasterPortParameters.v1(
Seq(TLMasterParameters.v1(
@@ -37,11 +22,8 @@ class MacTest(implicit p: Parameters) extends Mac{
))
)))
val tlBar = TLXbar()
tlBar := tlClientIONode
tlMasterNode := tlBar
ethReg.configNode := tlBar
ethReg.configNode := tlClientIONode
val intSinkNode = IntSinkNode(IntSinkPortSimple())
intSinkNode := ethReg.int_node

1
src/test/scala/gcd/test.scala
View File

@@ -2,6 +2,7 @@ package test
import MAC._
import BACK._
import Switch._
import chisel3._
import chisel3.stage._