完成编译，准备接入CPU查看信号逻辑

2023-10-17 16:38:18 +08:00
parent 7c71c005f8
commit 629d9486d1
8 changed files with 118 additions and 191 deletions
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -2,6 +2,7 @@ package test

 import MAC._
 import BACK._
+import Switch._

 import chisel3._
 import chisel3.stage._