完成编译，准备接入CPU查看信号逻辑

src/test/scala/gcd/Mac_test_top.scala

@@ -14,21 +14,6 @@ class MacTest(implicit p: Parameters) extends Mac{
 
 
 
-
-	val tlRAM = TLRAM(
-    address    = AddressSet(0x00000000L, 0x001FFFFFL),
-    cacheable  = false,
-    executable = false,
-    atomics    = false,
-    beatBytes  = 4,
-    sramReg = true,
-    devName = None,
-  )
-
-	tlRAM := tlClientNode
-
-
-
 	val tlClientIONode = 
 		TLClientNode(Seq(TLMasterPortParameters.v1(
 			Seq(TLMasterParameters.v1(
@@ -37,11 +22,8 @@ class MacTest(implicit p: Parameters) extends Mac{
 			))
 		)))
 
-	val tlBar = TLXbar()
 
-	tlBar := tlClientIONode
-	tlMasterNode := tlBar
-	ethReg.configNode  := tlBar
+	ethReg.configNode  := tlClientIONode
 
 	val intSinkNode = IntSinkNode(IntSinkPortSimple())
 	intSinkNode := ethReg.int_node

src/test/scala/gcd/test.scala

@@ -2,6 +2,7 @@ package test
 
 import MAC._
 import BACK._
+import Switch._
 
 import chisel3._
 import chisel3.stage._