From 628fdf2a4ae95fbb38033050986b5a23cb50ec43 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 20 May 2025 11:44:22 +0800 Subject: [PATCH] =?UTF-8?q?=E5=BC=80=E6=94=BE0x180=E8=87=AA=E5=AE=9A?= =?UTF-8?q?=E4=B9=89=E5=AF=84=E5=AD=98=E5=99=A8=E5=8C=BA=E5=9F=9F=EF=BC=8C?= =?UTF-8?q?=E4=B8=BB=E4=BB=8E=E5=9D=87=E5=8F=AF=E8=AE=BF=E9=97=AE?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 9678ca9..3c835cb 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -38,6 +38,8 @@ class CommonRegisterBundle extends Bundle{ val syncPoint = UInt(64.W) val syncPeroid = UInt(32.W) + val custom = Vec( 128, UInt(8.W) ) + // val smEnqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写） // val smDeqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写） @@ -355,7 +357,9 @@ abstract class InterfaceBase extends Module{ (addr === "h146".U & isSlvMode) -> sReg.syncOffset(3)(23,16), (addr === "h147".U & isSlvMode) -> sReg.syncOffset(3)(31,24), ) ++ - + ( 0 until 128 ).map{ i => + ( addr === ("h180".U + i.U ) ) -> cReg.custom(i) + } ++ ( 0 until 8 ).map{ i => ( addr === ("h302".U + (i*4).U) ) -> cReg.smTrigLen(i)(7,0) } ++ @@ -463,6 +467,13 @@ trait InterfaceMCUop{ this: InterfaceBase => mReg.rxSM := RegEnable( dataw(4,3), 0.U, isEnW & addrSel === "h20".U ) // mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrSel === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrSel === "h21".U ) ) + ( 0 until 128 ).map{ i => + cReg.custom(i) := RegEnable( dataw, 0.U, isEnW & (addrSel === ("h180".U + i.U)) ) + } + + + + mReg.rplTimeStampTx := Cat( RegEnable( dataw, 0.U, isEnW & addrSel === "h25".U ),