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上下行交换特性

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This commit is contained in:
Ruige Lee
2025-08-29 15:37:29 +08:00
parent 51d29f1dd7
commit 60eec33b2d
2 changed files with 67 additions and 30 deletions
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4
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -309,8 +309,8 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
}) ++
Seq(
(addr === "h4a".U ) -> cReg.dwupEx.extrace(0),
(addr === "h4c".U ) -> cReg.b8b4Sel.extrace(0),
(addr === "h4a".U ) -> cReg.dwupEx.extract(0),
(addr === "h4c".U ) -> cReg.b8b4Sel.extract(0),
(addr === "h4e".U ) -> cReg.cdrParam(7,0),
(addr === "h50".U ) -> cReg.anamuxSel,

93
src/main/scala/backBoard/shin/MstSlvSwitch.scala
View File

@@ -472,41 +472,78 @@ class MstSlvSwitch extends MstSlvSwitchBase
with MstSlvSwitchMaster
with MstSlvSwitchSlave
with MstSlvSwitchWatchDog{
val isDwUpEx = interface.cReg.dwupEx
val isDwUpEx = interface.io.cReg.dwupEx(15,8) === "h58".U && interface.io.cReg.dwupEx.extract(0)
when( interface.io.cReg.modeSel === false.B ){ //slave
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
when( ~isDwUpEx ){ //未交叉
when( interface.io.cReg.modeSel === false.B ){ //slave
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := false.B
when( slaveParser.io.isLoop ){ //回环
io.dDatOut := false.B
io.uDatOut := io.dDatIn
} .otherwise{ //非回环
io.dDatOut := io.dDatIn
io.uDatOut := io.uDatIn
}
} .otherwise{ //无硬件错误
when( slaveParser.io.isLoop ){ //回环
io.downCDRIn.serDat := io.dDatIn
io.upCDRIn.serDat := io.downCDROut.serDat
io.dDatOut := false.B
io.uDatOut := io.upCDROut.serDat
} .otherwise{ //非回环
io.downCDRIn.serDat := io.dDatIn
io.upCDRIn.serDat := io.uDatIn
io.dDatOut := io.downCDROut.serDat
io.uDatOut := io.upCDROut.serDat
}
}
} .otherwise{ //master
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := false.B
when( slaveParser.io.isLoop ){ //回环
io.dDatOut := false.B
io.uDatOut := io.dDatIn
} .otherwise{ //非回环
io.dDatOut := io.dDatIn
io.uDatOut := io.uDatIn
}
} .otherwise{ //无硬件错误
when( slaveParser.io.isLoop ){ //回环
io.downCDRIn.serDat := io.dDatIn
io.upCDRIn.serDat := io.downCDROut.serDat
io.dDatOut := false.B
io.uDatOut := io.upCDROut.serDat
} .otherwise{ //非回环
io.downCDRIn.serDat := io.dDatIn
io.upCDRIn.serDat := io.uDatIn
io.dDatOut := io.downCDROut.serDat
io.uDatOut := io.upCDROut.serDat
}
io.upCDRIn.serDat := io.uDatIn
io.dDatOut := io.downCDROut.serDat
io.uDatOut := false.B
}
} .otherwise{ //交叉
when( interface.io.cReg.modeSel === false.B ){ //slave
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
when( slaveParser.io.isLoop ){ //回环
io.dDatOut := io.uDatIn
io.uDatOut := false.B
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := false.B
} .otherwise{ //非回环
io.dDatOut := io.dDatIn
io.uDatOut := io.uDatIn
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := false.B
}
} .otherwise{ //无硬件错误
when( slaveParser.io.isLoop ){ //回环
io.downCDRIn.serDat := io.uDatIn
io.upCDRIn.serDat := io.downCDROut.serDat
io.uDatOut := false.B
io.dDatOut := io.upCDROut.serDat
} .otherwise{ //非回环
io.downCDRIn.serDat := io.uDatIn
io.upCDRIn.serDat := io.dDatIn
io.dDatOut := io.upCDROut.serDat
io.uDatOut := io.downCDROut.serDat
}
}
} .otherwise{ //master
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := io.dDatIn
io.uDatOut := io.downCDROut.serDat
io.dDatOut := false.B
}
} .otherwise{ //master
io.downCDRIn.serDat := false.B
io.upCDRIn.serDat := io.uDatIn
io.dDatOut := io.downCDROut.serDat
io.uDatOut := false.B
}
}