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rx: big-endian to little-endian

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RuigeLee
2023-09-21 16:55:22 +08:00
parent e42c6a3b11
commit 5ff118f527
1 changed files with 11 additions and 11 deletions
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22
src/main/scala/mac/MacTilelink.scala
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@@ -1316,7 +1316,7 @@ trait MacTileLinkRXClk{ this: MacTileLinkBase =>
withClockAndReset( io.MRxClk.asClock, reset.asAsyncReset ){ withClockAndReset( io.MRxClk.asClock, reset.asAsyncReset ){
val RxDataLatched2 = RegInit(0.U(32.W)); RxDataLatched2_rxclk := RxDataLatched2 val RxDataLatched2 = RegInit(0.U(32.W)); RxDataLatched2_rxclk := RxDataLatched2
val RxDataLatched1 = RegInit(0.U(24.W)) // Big Endian Byte Ordering[31:8] val RxDataLatched1 = RegInit(0.U(24.W)) // Little Endian Byte Ordering[23:0]
val RxValidBytes = RegInit(1.U(2.W)) val RxValidBytes = RegInit(1.U(2.W))
val RxByteCnt = RegInit(0.U(2.W)); RxByteCnt_rxclk := RxByteCnt val RxByteCnt = RegInit(0.U(2.W)); RxByteCnt_rxclk := RxByteCnt
val LastByteIn = RegInit(false.B); LastByteIn_rxclk := LastByteIn val LastByteIn = RegInit(false.B); LastByteIn_rxclk := LastByteIn
@@ -1380,16 +1380,16 @@ trait MacTileLinkRXClk{ this: MacTileLinkBase =>
when(io.RxValid & RxReady & ~LastByteIn){ when(io.RxValid & RxReady & ~LastByteIn){
when(io.RxStartFrm){ when(io.RxStartFrm){
RxDataLatched1 := Mux1H(Seq( RxDataLatched1 := Mux1H(Seq(
( RxPointerLSB_rst === 0.U ) -> Cat( io.RxData, RxDataLatched1(15,0)),// Big Endian Byte Ordering ( RxPointerLSB_rst === 0.U ) -> Cat(RxDataLatched1(23, 8), io.RxData),// Little Endian Byte Ordering
( RxPointerLSB_rst === 1.U ) -> Cat(RxDataLatched1(23,16), io.RxData, RxDataLatched1( 7,0)), ( RxPointerLSB_rst === 1.U ) -> Cat(RxDataLatched1(23,16), io.RxData, RxDataLatched1( 7,0)),
( RxPointerLSB_rst === 2.U ) -> Cat(RxDataLatched1(23, 8), io.RxData), ( RxPointerLSB_rst === 2.U ) -> Cat( io.RxData, RxDataLatched1(15,0)),
( RxPointerLSB_rst === 3.U ) -> RxDataLatched1, ( RxPointerLSB_rst === 3.U ) -> RxDataLatched1,
)) ))
} .elsewhen(RxEnableWindow){ } .elsewhen(RxEnableWindow){
RxDataLatched1 := Mux1H(Seq( RxDataLatched1 := Mux1H(Seq(
( RxByteCnt === 0.U ) -> Cat( io.RxData, RxDataLatched1(15,0)),// Big Endian Byte Ordering ( RxByteCnt === 0.U ) -> Cat(RxDataLatched1(23, 8), io.RxData),// Little Endian Byte Ordering
( RxByteCnt === 1.U ) -> Cat(RxDataLatched1(23,16), io.RxData, RxDataLatched1( 7,0)), ( RxByteCnt === 1.U ) -> Cat(RxDataLatched1(23,16), io.RxData, RxDataLatched1( 7,0)),
( RxByteCnt === 2.U ) -> Cat(RxDataLatched1(23, 8), io.RxData), ( RxByteCnt === 2.U ) -> Cat( io.RxData, RxDataLatched1(15,0)),
( RxByteCnt === 3.U ) -> RxDataLatched1, ( RxByteCnt === 3.U ) -> RxDataLatched1,
)) ))
} }
@@ -1398,13 +1398,13 @@ trait MacTileLinkRXClk{ this: MacTileLinkBase =>
// Assembling data that will be written to the rx_fifo // Assembling data that will be written to the rx_fifo
when(SetWriteRxDataToFifo & ~ShiftWillEnd){ when(SetWriteRxDataToFifo & ~ShiftWillEnd){
RxDataLatched2 := Cat(RxDataLatched1, io.RxData)// Big Endian Byte Ordering RxDataLatched2 := Cat(io.RxData, RxDataLatched1)// Little Endian Byte Ordering
} .elsewhen(SetWriteRxDataToFifo & ShiftWillEnd){ } .elsewhen(SetWriteRxDataToFifo & ShiftWillEnd){
RxDataLatched2 := Mux1H(Seq( RxDataLatched2 := Mux1H(Seq( // Little Endian Byte Ordering
( RxValidBytes === 0.U ) -> Cat(RxDataLatched1, io.RxData), ( RxValidBytes === 0.U ) -> Cat(io.RxData, RxDataLatched1),
( RxValidBytes === 1.U ) -> Cat(RxDataLatched1(23,16), 0.U(24.W)), ( RxValidBytes === 1.U ) -> Cat(0.U(24.W), RxDataLatched1(7,0) ),
( RxValidBytes === 2.U ) -> Cat(RxDataLatched1(23, 8), 0.U(16.W)), ( RxValidBytes === 2.U ) -> Cat(0.U(16.W), RxDataLatched1(15, 0) ),
( RxValidBytes === 3.U ) -> Cat(RxDataLatched1, 0.U(8.W)), ( RxValidBytes === 3.U ) -> Cat(0.U(8.W), RxDataLatched1 ),
)) ))
} }