mac dma 抽象成node
This commit is contained in:
RuigeLee
@@ -1,567 +0,0 @@
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package MAC
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import chisel3._
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import chisel3.util._
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import Switch._
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class MII extends Bundle with MDIO{
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// Tx
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val mtx_clk_pad_i = Input(Bool())
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val mtxd_pad_o = Output(UInt(4.W))
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val mtxen_pad_o = Output(Bool())
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val mtxerr_pad_o = Output(Bool())
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// Rx
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val mrx_clk_pad_i = Input(Bool())
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val mrxd_pad_i = Input(UInt(4.W))
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val mrxdv_pad_i = Input(Bool())
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val mrxerr_pad_i = Input(Bool())
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// Common Tx and Rx
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val mcoll_pad_i = Input(Bool())
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val mcrs_pad_i = Input(Bool())
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}
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class MacIO extends Bundle{
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val mii = new MII
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val cfg = Flipped(new Mac_Config_Bundle)
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val rxEnq = Decoupled(new Mac_Stream_Bundle)
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val txDeq = Flipped(Decoupled(new Mac_Stream_Bundle))
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// val int_o = Output(Bool())
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val isLoopBack = Output(Bool())
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val asyncReset = Input(AsyncReset())
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}
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class Mac extends Module{
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val io = IO(new MacIO)
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val r_ClkDiv = Wire(UInt(8.W))
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val r_MiiNoPre = Wire(Bool())
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val r_CtrlData = Wire(UInt(16.W))
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val r_FIAD = Wire(UInt(5.W))
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val r_RGAD = Wire(UInt(5.W))
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val r_WCtrlData = Wire(Bool())
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val r_RStat = Wire(Bool())
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val r_ScanStat = Wire(Bool())
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val NValid_stat = Wire(Bool())
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val Busy_stat = Wire(Bool())
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val LinkFail = Wire(Bool())
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val Prsd = Wire(UInt(16.W))
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val WCtrlDataStart = Wire(Bool())
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val RStatStart = Wire(Bool())
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val UpdateMIIRX_DATAReg = Wire(Bool())
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dontTouch( r_ClkDiv )
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dontTouch( r_MiiNoPre )
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dontTouch( r_CtrlData )
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dontTouch( r_FIAD )
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dontTouch( r_RGAD )
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dontTouch( r_WCtrlData )
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dontTouch( r_RStat )
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dontTouch( r_ScanStat )
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dontTouch( NValid_stat )
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dontTouch( Busy_stat )
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dontTouch( LinkFail )
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dontTouch( Prsd )
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dontTouch( WCtrlDataStart )
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dontTouch( RStatStart )
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dontTouch( UpdateMIIRX_DATAReg )
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val TxStartFrm = Wire(Bool())
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val TxEndFrm = Wire(Bool())
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val TxUsedData = Wire(Bool())
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val TxData = Wire(UInt(8.W))
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val TxAbort = Wire(Bool())
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val TxDone = Wire(Bool())
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dontTouch(TxStartFrm)
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dontTouch(TxEndFrm )
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dontTouch(TxUsedData)
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dontTouch(TxData )
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dontTouch(TxAbort )
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dontTouch(TxDone )
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// Connecting Miim module
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val miim = Module(new MIIM)
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miim.io.Divider := r_ClkDiv
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miim.io.NoPre := r_MiiNoPre
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miim.io.WCtrlData := r_WCtrlData
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miim.io.CtrlData := r_CtrlData
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miim.io.Fiad := r_FIAD
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miim.io.Rgad := r_RGAD
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miim.io.RStat := r_RStat
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miim.io.ScanStat := r_ScanStat
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miim.io.mdi := io.mii.mdi
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Busy_stat := miim.io.Busy
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LinkFail := miim.io.LinkFail
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NValid_stat := miim.io.Nvalid
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Prsd := miim.io.Prsd
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WCtrlDataStart := miim.io.WCtrlDataStart
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RStatStart := miim.io.RStatStart
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UpdateMIIRX_DATAReg := miim.io.UpdateMIIRX_DATAReg
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io.mii.mdc := miim.io.mdc
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io.mii.mdo := miim.io.mdo
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io.mii.mdoEn := miim.io.mdoEn
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val r_LoopBck = Wire(Bool())
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val r_TxEn = Wire(Bool())
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val r_RxEn = Wire(Bool())
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val MRxDV_Lb = Wire(Bool())
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val MRxErr_Lb = Wire(Bool())
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val MRxD_Lb = Wire(UInt(4.W))
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val Transmitting = Wire(Bool())
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val DribbleNibble = Wire(Bool())
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val LoadRxStatus = Wire(Bool())
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val r_HASH0 = Wire(UInt(32.W))
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val r_HASH1 = Wire(UInt(32.W))
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val r_IPGT = Wire(UInt(7.W))
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val r_IPGR1 = Wire(UInt(7.W))
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val r_IPGR2 = Wire(UInt(7.W))
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val r_CollValid = Wire(UInt(6.W))
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val r_ExDfrEn = Wire(Bool())
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val r_IFG = Wire(Bool())
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val TxB_IRQ = Wire(Bool())
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val TxE_IRQ = Wire(Bool())
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val RxB_IRQ = Wire(Bool())
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val RxE_IRQ = Wire(Bool())
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val Busy_IRQ = Wire(Bool())
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val r_FullD = Wire(Bool())
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val r_NoPre = Wire(Bool())
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val StartTxDone = Wire(Bool())
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val PerPacketCrcEn = Wire(Bool())
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val LateCollision = Wire(Bool())
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val DeferIndication = Wire(Bool())
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val LateCollLatched = Wire(Bool())
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val DeferLatched = Wire(Bool())
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val RstDeferLatched = Wire(Bool())
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val CarrierSenseLost = Wire(Bool())
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dontTouch(r_LoopBck )
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dontTouch(r_TxEn )
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dontTouch(r_RxEn )
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dontTouch(MRxDV_Lb )
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dontTouch(MRxErr_Lb )
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dontTouch(MRxD_Lb )
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dontTouch(Transmitting )
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dontTouch(DribbleNibble )
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dontTouch(LoadRxStatus )
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dontTouch(r_HASH0 )
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dontTouch(r_HASH1 )
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dontTouch(r_IPGT )
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dontTouch(r_IPGR1 )
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dontTouch(r_IPGR2 )
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dontTouch(r_CollValid )
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dontTouch(r_ExDfrEn )
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dontTouch(r_IFG )
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dontTouch(TxB_IRQ )
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dontTouch(TxE_IRQ )
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dontTouch(RxB_IRQ )
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dontTouch(RxE_IRQ )
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dontTouch(Busy_IRQ )
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dontTouch(r_FullD )
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dontTouch(r_NoPre )
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dontTouch(StartTxDone )
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dontTouch(PerPacketCrcEn )
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dontTouch(LateCollision )
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dontTouch(DeferIndication )
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dontTouch(LateCollLatched )
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dontTouch(DeferLatched )
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dontTouch(RstDeferLatched )
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dontTouch(CarrierSenseLost )
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io.cfg.WCtrlDataStart := WCtrlDataStart
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io.cfg.RStatStart := RStatStart
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io.cfg.UpdateMIIRX_DATAReg := UpdateMIIRX_DATAReg
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io.cfg.Prsd := Prsd
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io.cfg.NValid_stat := NValid_stat
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io.cfg.Busy_stat := Busy_stat
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io.cfg.LinkFail := LinkFail
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io.cfg.TxB_IRQ := TxB_IRQ
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io.cfg.TxE_IRQ := TxE_IRQ
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io.cfg.RxB_IRQ := RxB_IRQ
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io.cfg.RxE_IRQ := RxE_IRQ
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io.cfg.Busy_IRQ := Busy_IRQ
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io.cfg.StartTxDone := StartTxDone
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io.cfg.TxClk := io.mii.mtx_clk_pad_i
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io.cfg.RxClk := io.mii.mrx_clk_pad_i
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r_FullD := io.cfg.r_FullD
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r_ExDfrEn := io.cfg.r_ExDfrEn
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r_LoopBck := io.cfg.r_LoopBck
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r_IFG := io.cfg.r_IFG
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r_NoPre := io.cfg.r_NoPre
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r_TxEn := io.cfg.r_TxEn
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r_RxEn := io.cfg.r_RxEn
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r_HASH0 := io.cfg.r_HASH0
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r_HASH1 := io.cfg.r_HASH1
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r_IPGT := io.cfg.r_IPGT
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r_IPGR1 := io.cfg.r_IPGR1
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r_IPGR2 := io.cfg.r_IPGR2
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r_CollValid := io.cfg.r_CollValid
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r_MiiNoPre := io.cfg.r_MiiNoPre
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r_ClkDiv := io.cfg.r_ClkDiv
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r_WCtrlData := io.cfg.r_WCtrlData
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r_RStat := io.cfg.r_RStat
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r_ScanStat := io.cfg.r_ScanStat
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r_RGAD := io.cfg.r_RGAD
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r_FIAD := io.cfg.r_FIAD
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r_CtrlData := io.cfg.r_CtrlData
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val RxData = Wire(UInt(8.W))
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val RxValid = Wire(Bool())
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val RxStartFrm = Wire(Bool())
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val RxEndFrm = Wire(Bool())
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val WillTransmit = Wire(Bool())
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val ResetCollision = Wire(Bool())
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val LatchedCrcError = Wire(Bool())
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val RxLateCollision = Wire(Bool())
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val StartTxAbort = Wire(Bool())
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val MaxCollisionOccured = Wire(Bool())
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val RetryLimit = Wire(Bool())
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val StatePreamble = Wire(Bool())
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val StateData = Wire(UInt(2.W))
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dontTouch(RxData )
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dontTouch(RxValid )
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dontTouch(RxStartFrm )
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dontTouch(RxEndFrm )
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dontTouch(WillTransmit )
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dontTouch(ResetCollision )
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dontTouch(LatchedCrcError )
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dontTouch(RxLateCollision )
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dontTouch(StartTxAbort )
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dontTouch(MaxCollisionOccured )
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dontTouch(RetryLimit )
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dontTouch(StatePreamble )
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dontTouch(StateData )
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val TxCarrierSense = Wire(Bool())
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val Collision = Wire(Bool())
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val CarrierSense_Tx2 = Wire(Bool())
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val RxEnSync = Wire(Bool())
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dontTouch(TxCarrierSense )
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dontTouch(Collision )
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dontTouch(CarrierSense_Tx2)
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dontTouch(RxEnSync )
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io.isLoopBack := r_LoopBck
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// Muxed MII receive data valid
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MRxDV_Lb := Mux(r_LoopBck, io.mii.mtxen_pad_o, io.mii.mrxdv_pad_i & RxEnSync)
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// Muxed MII Receive Error
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MRxErr_Lb := Mux(r_LoopBck, io.mii.mtxerr_pad_o, io.mii.mrxerr_pad_i & RxEnSync)
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// Muxed MII Receive Data
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MRxD_Lb := Mux(r_LoopBck, io.mii.mtxd_pad_o, io.mii.mrxd_pad_i)
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val txethmac = withClockAndReset(io.mii.mtx_clk_pad_i.asClock, io.asyncReset)( Module(new MacTx))
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txethmac.io.TxStartFrm := TxStartFrm
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txethmac.io.TxEndFrm := TxEndFrm
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txethmac.io.TxData := TxData
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txethmac.io.CarrierSense := TxCarrierSense
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txethmac.io.Collision := Collision
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txethmac.io.CrcEn := PerPacketCrcEn
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txethmac.io.FullD := r_FullD
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txethmac.io.IPGT := r_IPGT
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txethmac.io.IPGR1 := r_IPGR1
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txethmac.io.IPGR2 := r_IPGR2
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txethmac.io.CollValid := r_CollValid
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txethmac.io.ExDfrEn := r_ExDfrEn
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io.mii.mtxd_pad_o := txethmac.io.MTxD
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io.mii.mtxen_pad_o := txethmac.io.MTxEn
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io.mii.mtxerr_pad_o := txethmac.io.MTxErr
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TxDone := txethmac.io.TxDone
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TxAbort := txethmac.io.TxAbort
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TxUsedData := txethmac.io.TxUsedData
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WillTransmit := txethmac.io.WillTransmit
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ResetCollision := txethmac.io.ResetCollision
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StartTxDone := txethmac.io.StartTxDone
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StartTxAbort := txethmac.io.StartTxAbort
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MaxCollisionOccured := txethmac.io.MaxCollisionOccured
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LateCollision := txethmac.io.LateCollision
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DeferIndication := txethmac.io.DeferIndication
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StatePreamble := txethmac.io.StatePreamble
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StateData := txethmac.io.StateData
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val RxByteCnt = Wire(UInt(16.W))
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val RxByteCntEq0 = Wire(Bool())
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val RxByteCntGreat2 = Wire(Bool())
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val RxCrcError = Wire(Bool())
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val RxStateIdle = Wire(Bool())
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val RxStatePreamble = Wire(Bool())
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val RxStateSFD = Wire(Bool())
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val RxStateData = Wire(UInt(2.W))
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dontTouch(RxByteCnt )
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dontTouch(RxByteCntEq0 )
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dontTouch(RxByteCntGreat2 )
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dontTouch(RxCrcError )
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dontTouch(RxStateIdle )
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dontTouch(RxStatePreamble )
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dontTouch(RxStateSFD )
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dontTouch(RxStateData )
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val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( Module(new MacRx))
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rxethmac.io.MRxDV := MRxDV_Lb
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rxethmac.io.MRxD := MRxD_Lb
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rxethmac.io.Transmitting := Transmitting
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rxethmac.io.r_IFG := r_IFG
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rxethmac.io.r_HASH0 := r_HASH0
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rxethmac.io.r_HASH1 := r_HASH1
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RxData := rxethmac.io.RxData
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RxValid := rxethmac.io.RxValid
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RxStartFrm := rxethmac.io.RxStartFrm
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RxEndFrm := rxethmac.io.RxEndFrm
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RxByteCnt := rxethmac.io.ByteCnt
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RxByteCntEq0 := rxethmac.io.ByteCntEq0
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RxByteCntGreat2 := rxethmac.io.ByteCntGreat2
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RxCrcError := rxethmac.io.CrcError
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RxStateIdle := rxethmac.io.StateIdle
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RxStatePreamble := rxethmac.io.StatePreamble
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RxStateSFD := rxethmac.io.StateSFD
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RxStateData := rxethmac.io.StateData
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withClockAndReset( io.mii.mtx_clk_pad_i.asClock, reset.asAsyncReset ) {
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// MII Carrier Sense Synchronization
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CarrierSense_Tx2 := ShiftRegister(io.mii.mcrs_pad_i, 2, false.B, true.B)
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TxCarrierSense := ~r_FullD & CarrierSense_Tx2
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val Collision_Tx1 = RegNext(io.mii.mcoll_pad_i, false.B)
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val Collision_Tx2 = RegInit(false.B)
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when(ResetCollision){
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Collision_Tx2 := false.B
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} .elsewhen(Collision_Tx1){
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Collision_Tx2 := true.B
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}
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// Synchronized Collision
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Collision := ~r_FullD & Collision_Tx2
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}
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withClockAndReset( io.mii.mrx_clk_pad_i.asClock, reset.asAsyncReset ) {
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val WillTransmit_q = ShiftRegister(WillTransmit, 2, false.B, true.B)
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Transmitting := ~r_FullD & WillTransmit_q
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RxEnSync := RegEnable( ShiftRegister(r_RxEn, 2), false.B, ~io.mii.mrxdv_pad_i)
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}
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val macstatus = Module(new MacStatus)
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macstatus.io.asyncReset := io.asyncReset
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macstatus.io.MRxClk := io.mii.mrx_clk_pad_i
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macstatus.io.RxCrcError := RxCrcError
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macstatus.io.MRxErr := MRxErr_Lb
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macstatus.io.MRxDV := MRxDV_Lb
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macstatus.io.RxStateSFD := RxStateSFD
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macstatus.io.RxStateData := RxStateData
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macstatus.io.RxStatePreamble := RxStatePreamble
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macstatus.io.RxStateIdle := RxStateIdle
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macstatus.io.Transmitting := Transmitting
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macstatus.io.RxByteCnt := RxByteCnt
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macstatus.io.RxByteCntEq0 := RxByteCntEq0
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macstatus.io.RxByteCntGreat2 := RxByteCntGreat2
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macstatus.io.MRxD := MRxD_Lb
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macstatus.io.Collision := io.mii.mcoll_pad_i
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macstatus.io.CollValid := r_CollValid
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macstatus.io.StartTxDone := StartTxDone
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macstatus.io.StartTxAbort := StartTxAbort
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macstatus.io.MTxClk := io.mii.mtx_clk_pad_i
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macstatus.io.MaxCollisionOccured := MaxCollisionOccured
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macstatus.io.LateCollision := LateCollision
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macstatus.io.DeferIndication := DeferIndication
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macstatus.io.TxStartFrm := TxStartFrm
|
||||
macstatus.io.StatePreamble := StatePreamble
|
||||
macstatus.io.StateData := StateData
|
||||
macstatus.io.CarrierSense := CarrierSense_Tx2
|
||||
macstatus.io.Loopback := r_LoopBck
|
||||
macstatus.io.r_FullD := r_FullD
|
||||
macstatus.io.RstDeferLatched := RstDeferLatched
|
||||
|
||||
LatchedCrcError := macstatus.io.LatchedCrcError
|
||||
RxLateCollision := macstatus.io.RxLateCollision
|
||||
DribbleNibble := macstatus.io.DribbleNibble
|
||||
LoadRxStatus := macstatus.io.LoadRxStatus
|
||||
RetryLimit := macstatus.io.RetryLimit
|
||||
LateCollLatched := macstatus.io.LateCollLatched
|
||||
DeferLatched := macstatus.io.DeferLatched
|
||||
CarrierSenseLost := macstatus.io.CarrierSenseLost
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
val macTileLinkTx = Module(new MacTileLinkTx)
|
||||
|
||||
RstDeferLatched := macTileLinkTx.io.RstDeferLatched
|
||||
TxStartFrm := macTileLinkTx.io.TxStartFrm
|
||||
TxEndFrm := macTileLinkTx.io.TxEndFrm
|
||||
TxData := macTileLinkTx.io.TxData
|
||||
macTileLinkTx.io.TxUsedData := TxUsedData
|
||||
macTileLinkTx.io.TxAbort := TxAbort
|
||||
macTileLinkTx.io.TxDone := TxDone
|
||||
|
||||
macTileLinkTx.io.RetryLimit := RetryLimit
|
||||
macTileLinkTx.io.LateCollLatched := LateCollLatched
|
||||
macTileLinkTx.io.DeferLatched := DeferLatched
|
||||
macTileLinkTx.io.CarrierSenseLost := CarrierSenseLost
|
||||
PerPacketCrcEn := macTileLinkTx.io.PerPacketCrcEn
|
||||
|
||||
macTileLinkTx.io.r_TxEn := r_TxEn
|
||||
|
||||
io.txDeq <> macTileLinkTx.io.txDeq
|
||||
|
||||
macTileLinkTx.io.MTxClk := io.mii.mtx_clk_pad_i
|
||||
macTileLinkTx.io.asyncReset := io.asyncReset
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
val macTileLinkRx = Module(new MacTileLinkRx)
|
||||
macTileLinkRx.io.DribbleNibble := DribbleNibble
|
||||
macTileLinkRx.io.LatchedCrcError := LatchedCrcError
|
||||
macTileLinkRx.io.RxLateCollision := RxLateCollision
|
||||
macTileLinkRx.io.LoadRxStatus := LoadRxStatus
|
||||
|
||||
macTileLinkRx.io.RxData := RxData
|
||||
macTileLinkRx.io.RxValid := RxValid
|
||||
macTileLinkRx.io.RxStartFrm := RxStartFrm
|
||||
macTileLinkRx.io.RxEndFrm := RxEndFrm
|
||||
|
||||
Busy_IRQ := macTileLinkRx.io.Busy_IRQ
|
||||
|
||||
macTileLinkRx.io.r_RxEn := r_RxEn
|
||||
|
||||
macTileLinkRx.io.rxEnq <> io.rxEnq
|
||||
|
||||
macTileLinkRx.io.MRxClk := io.mii.mrx_clk_pad_i
|
||||
macTileLinkRx.io.asyncReset := io.asyncReset
|
||||
|
||||
TxB_IRQ := false.B
|
||||
TxE_IRQ := false.B
|
||||
RxB_IRQ := false.B
|
||||
RxE_IRQ := false.B
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -1,94 +0,0 @@
|
||||
package MAC
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import Switch._
|
||||
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import org.chipsalliance.cde.config._
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
abstract class MacTileLinkBase() extends Module{
|
||||
|
||||
class MacTileLinkIO extends Bundle{
|
||||
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
val io = IO(new MacTileLinkIO)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
class MacTileLink() extends MacTileLinkBase(){
|
||||
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user