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mac dma 抽象成node

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This commit is contained in:
RuigeLee
2023-11-01 14:48:03 +08:00
parent 7c78948415
commit 5e50dc3148
6 changed files with 542 additions and 690 deletions
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20
src/main/scala/Switch/Switch.scala
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@@ -44,7 +44,7 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out
val ( dma_bus, dma_edge ) = outer.tlClientNode.out.head
val mac = ( 0 until chn ).map{ i =>
Module(new Mac)
Module(new MacNode)
}
( 0 until chn ).map{ i =>
@@ -56,11 +56,9 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out
outer.ethReg.module.io.asyncReset := io.asyncReset
outer.ethReg.module.io.viewAsSupertype(new Mac_Config_Bundle) <> mac(0).io.cfg
val dmaMst = Module(new DMAMst(dma_edge))
dmaMst.io.rxEnq(0) <> mac(0).io.rxEnq
dmaMst.io.txDeq(0) <> mac(0).io.txDeq
val dmaMst = Module(new DmaNode(dma_edge))
dmaMst.io.triTx := outer.ethReg.module.io.triTx
outer.ethReg.module.io.triRx := dmaMst.io.triRx
@@ -71,17 +69,6 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out
dmaMst.io.r_TxLen := outer.ethReg.module.io.r_TxLen
outer.ethReg.module.io.r_RxLen := dmaMst.io.r_RxLen
dmaMst.io.dmaMst.D.bits := dma_bus.d.bits
dmaMst.io.dmaMst.D.valid := dma_bus.d.valid
dma_bus.d.ready := dmaMst.io.dmaMst.D.ready
@@ -94,7 +81,8 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out
dmaMst.ex.tx <> mac(0).ex.rx
dmaMst.ex.rx <> mac(0).ex.tx