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清理代码

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This commit is contained in:
RuigeLee
2024-11-05 11:13:36 +08:00
parent f89f48f951
commit 5d6151b2ac
4 changed files with 2 additions and 139 deletions
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16
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -14,9 +14,6 @@ class CDRInIO extends Bundle{
abstract class CDRInBase extends Module{
def sampleRate: Int = 4
// require( sampleRate == 4 )
// require( (sampleRate % 2) == 1 )
val io: CDRInIO = IO(new CDRInIO)
@@ -25,8 +22,6 @@ abstract class CDRInBase extends Module{
trait CDRInOverSample{ this: CDRInBase =>
val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
// val arbResult = VecInit(sampleReg).count( (x:Bool) => (x === true.B) ) > ((sampleRate-1) / 2).U
val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) }
val arbSel = Reg(UInt( log2Ceil(sampleRate).W ))
@@ -45,17 +40,6 @@ trait CDRInOverSample{ this: CDRInBase =>
isArbLock := false.B
}
// val arbResult =
// (sampleReg(3) & sampleReg(2) & sampleReg(1)) |
// (sampleReg(3) & sampleReg(2) & sampleReg(0)) |
// (sampleReg(3) & sampleReg(1) & sampleReg(0)) |
// (sampleReg(2) & sampleReg(1) & sampleReg(0))
val syncSerDat = ShiftRegister(
PriorityMux( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } )
, 2 )

81
src/main/scala/backBoard/pico/BackSystem.scala
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@@ -46,56 +46,6 @@ class BackCfg extends Config((_, _, _) => {
class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameters {
// val coreClientNode = TLClientNode(Seq(TLMasterPortParameters.v1(
// Seq(TLMasterParameters.v1(
// name = "core",
// sourceId = IdRange(0, 1),
// ))
// )))
// val sram = LazyModule(new TLRAM(
// address = AddressSet(0x00000000L, 0xfffL),
// cacheable = false,
// executable = true,
// atomics = false,
// beatBytes = 4,
// sramReg = false, // drive SRAM data output directly into a register => 1 cycle longer response
// ))
// val cdrNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
// managers = Seq(TLSlaveParameters.v1(
// address = Seq(AddressSet(0x00001000L, 0xffL)),
// regionType = RegionType.UNCACHED,
// executable = false,
// supportsGet = TransferSizes(32/8, 32/8),
// supportsPutFull = TransferSizes(32/8, 32/8),
// supportsPutPartial = TransferSizes(32/8, 32/8)
// )),
// beatBytes = 32/8)))
// val gpioNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
// managers = Seq(TLSlaveParameters.v1(
// address = Seq(AddressSet(0x0002000L, 0xffL)),
// regionType = RegionType.UNCACHED,
// executable = false,
// supportsGet = TransferSizes(32/8, 32/8),
// supportsPutFull = TransferSizes(32/8, 32/8),
// supportsPutPartial = TransferSizes(32/8, 32/8)
// )),
// beatBytes = 32/8)))
// val xbar = TLXbar(
// //policy = TLArbiter.lowestIndexFirst
// )
// xbar := coreClientNode
// cdrNode := xbar
// sram.node := xbar
// gpioNode := xbar
lazy val module: BackSysImp = new BackSysImp(this)
}
@@ -116,15 +66,10 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame
val DCIn = Input(Bool())
}
// val ( core_bus, core_edge ) = outer.coreClientNode.out.head
// val ( cdr_bus, cdr_edge ) = outer.cdrNode.in.head
// val ( gpio_bus, gpio_edge ) = outer.gpioNode.in.head
val io: BackSysIO = IO(new BackSysIO)
val pico = Module(new Picorv32_mem )
// val pico = Module(new Picorv32_tl(edge = core_edge))
val cdr = Module(new TLCDR() )
val gpio = Module(new SimpleGpio() )
val sram = Module(new SimpleSRAM)
@@ -192,33 +137,7 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame
assert( pico.io.mem.wstrb.andR | ~pico.io.mem.wstrb.orR )
// pico.io.tld.bits := core_bus.d.bits
// pico.io.tld.valid := core_bus.d.valid
// core_bus.d.ready := pico.io.tld.ready
// core_bus.a.valid := pico.io.tla.valid
// core_bus.a.bits := pico.io.tla.bits
// pico.io.tla.ready := core_bus.a.ready
// cdr.io.tla.valid := cdr_bus.a.valid & cdr_bus.a.bits.address(7) === "h0".U
// cdr.io.tla.bits := cdr_bus.a.bits
// cdr_bus.a.ready := cdr.io.tla.ready
// cdr_bus.d.valid := cdr.io.tld.valid
// cdr_bus.d.bits := cdr.io.tld.bits
// cdr.io.tld.ready := cdr_bus.d.ready
// gpio.io.tla.valid := gpio_bus.a.valid
// gpio.io.tla.bits := gpio_bus.a.bits
// gpio_bus.a.ready := gpio.io.tla.ready
// gpio_bus.d.valid := gpio.io.tld.valid
// gpio_bus.d.bits := gpio.io.tld.bits
// gpio.io.tld.ready := gpio_bus.d.ready
}

16
src/main/scala/backBoard/pico/SimpleSRAM.scala
View File

@@ -20,8 +20,6 @@ class SimpleSRAM()(implicit p: Parameters) extends BackModule{
io.mem.rdata := DontCare
// when(io.mem.valid) {
when( io.mem.valid & io.mem.wstrb.extract(0) ){
mem.write( io.mem.addr(11,2), io.mem.wdata )
@@ -30,17 +28,6 @@ class SimpleSRAM()(implicit p: Parameters) extends BackModule{
io.mem.rdata := mem.read(io.mem.addr(11,2), true.B)
// when ( io.mem.wstrb =/= 0.U ) {
// when(io.mem.wstrb.extract(0)) { mem(io.mem.addr(11,2))(0) := io.mem.wdata(7,0) }
// when(io.mem.wstrb.extract(1)) { mem(io.mem.addr(11,2))(1) := io.mem.wdata(15,8) }
// when(io.mem.wstrb.extract(2)) { mem(io.mem.addr(11,2))(2) := io.mem.wdata(23,16) }
// when(io.mem.wstrb.extract(3)) { mem(io.mem.addr(11,2))(3) := io.mem.wdata(31,24) }
// } .otherwise { io.mem.rdata := Cat( mem(io.mem.addr(11,2)).reverse ) }
// }
val isReadAck = RegInit(false.B)
when( io.mem.fire ){
isReadAck := false.B
@@ -52,7 +39,4 @@ class SimpleSRAM()(implicit p: Parameters) extends BackModule{
( io.mem.wstrb =/= 0.U & true.B ) |
( io.mem.wstrb === 0.U & isReadAck )
}

24
src/main/scala/backBoard/pico/TLCDR.scala
View File

@@ -127,14 +127,12 @@ trait TLCDRRx{ this: TLCDRBase =>
val isTLReadRxFifo = io.mem.fire & io.mem.addr(4,0) === "h1c".U & ( io.mem.wstrb === 0.U )
val rxLen = RegInit(0.U(12.W))
// val isRxBusy = RegInit(false.B)
val isRxValid = rxFifo.io.enq.fire
val isRxError = RegInit(false.B)
val isAxisEnd = RegInit(false.B)
val isRxEnd = isAxisEnd & ~rxFifo.io.deq.valid
val intRxError = ~RegNext(isRxError, false.B) & isRxError
// val intRxValid = ~RegNext(isRxValid, false.B) & isRxValid
val intRxStart = rxLen === 0.U & CDRIn.io.axis.fire
val intRxEnd = ~RegNext(isRxEnd, false.B) & isRxEnd
@@ -155,13 +153,6 @@ trait TLCDRRx{ this: TLCDRBase =>
rxCnt := rxCnt + 1.U
rxData := Cat( rxData, CDRIn.io.axis.bits.tdata )
// PriorityMux(Seq(
// (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(16.W) /*,0.U(8.W)*/ ),
// (rxCnt === 1.U) -> Cat( rxData(23,16), CDRIn.io.axis.bits.tdata, 0.U(8.W) /*,0.U(8.W)*/ ),
// (rxCnt === 2.U) -> Cat( rxData(23, 8), CDRIn.io.axis.bits.tdata /*,0.U(8.W)*/ ),
// // (rxCnt === 3.U) -> Cat( rxData(31,8) , CDRIn.io.axis.bits.tdata ),
// ))
}
when( isTLWriteSoftReset ){
@@ -173,12 +164,6 @@ trait TLCDRRx{ this: TLCDRBase =>
rxFifo.io.enq.valid := CDRIn.io.axis.fire & rxCnt === 3.U
rxFifo.io.enq.bits := Cat( rxData(23, 0) , CDRIn.io.axis.bits.tdata )
// PriorityMux(Seq(
// (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(24.W) ),
// (rxCnt === 1.U) -> Cat( rxData(23,16), CDRIn.io.axis.bits.tdata, 0.U(16.W) ),
// (rxCnt === 2.U) -> Cat( rxData(23, 8), CDRIn.io.axis.bits.tdata, 0.U(8.W ) ),
// (rxCnt === 3.U) -> Cat( rxData(23, 0) , CDRIn.io.axis.bits.tdata ),
// ))
assert( ~(( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast) & rxCnt =/= 3.U), "Assert Failed! Rx must 4-byte Align!" )
CDRIn.io.axis.ready := true.B
@@ -203,10 +188,6 @@ class TLCDR()(implicit p: Parameters) extends TLCDRBase() with TLCDRTx with TLCD
val isWriteTransDir = io.mem.fire & io.mem.addr(4,0) === "hc".U & io.mem.wstrb =/= 0.U
when( isWriteTransDir ){
dirSel := io.mem.wdata
}
@@ -215,8 +196,6 @@ class TLCDR()(implicit p: Parameters) extends TLCDRBase() with TLCDRTx with TLCD
( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready) |
( io.mem.wstrb === 0.U & Mux( io.mem.addr(4,0) === "h1c".U, rxFifo.io.deq.valid, true.B ) )
io.interrupt(0) := intTxEnd
io.interrupt(1) := intRxError
io.interrupt(2) := intRxStart
@@ -230,9 +209,6 @@ class TLCDR()(implicit p: Parameters) extends TLCDRBase() with TLCDRTx with TLCD
isTLReadRxFifo -> rxFifo.io.deq.bits
))
}