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清理代码

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This commit is contained in:
RuigeLee
2024-11-05 11:13:36 +08:00
parent f89f48f951
commit 5d6151b2ac
4 changed files with 2 additions and 139 deletions
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24
src/main/scala/backBoard/pico/TLCDR.scala
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@@ -127,14 +127,12 @@ trait TLCDRRx{ this: TLCDRBase =>
val isTLReadRxFifo = io.mem.fire & io.mem.addr(4,0) === "h1c".U & ( io.mem.wstrb === 0.U )
val rxLen = RegInit(0.U(12.W))
// val isRxBusy = RegInit(false.B)
val isRxValid = rxFifo.io.enq.fire
val isRxError = RegInit(false.B)
val isAxisEnd = RegInit(false.B)
val isRxEnd = isAxisEnd & ~rxFifo.io.deq.valid
val intRxError = ~RegNext(isRxError, false.B) & isRxError
// val intRxValid = ~RegNext(isRxValid, false.B) & isRxValid
val intRxStart = rxLen === 0.U & CDRIn.io.axis.fire
val intRxEnd = ~RegNext(isRxEnd, false.B) & isRxEnd
@@ -155,13 +153,6 @@ trait TLCDRRx{ this: TLCDRBase =>
rxCnt := rxCnt + 1.U
rxData := Cat( rxData, CDRIn.io.axis.bits.tdata )
// PriorityMux(Seq(
// (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(16.W) /*,0.U(8.W)*/ ),
// (rxCnt === 1.U) -> Cat( rxData(23,16), CDRIn.io.axis.bits.tdata, 0.U(8.W) /*,0.U(8.W)*/ ),
// (rxCnt === 2.U) -> Cat( rxData(23, 8), CDRIn.io.axis.bits.tdata /*,0.U(8.W)*/ ),
// // (rxCnt === 3.U) -> Cat( rxData(31,8) , CDRIn.io.axis.bits.tdata ),
// ))
}
when( isTLWriteSoftReset ){
@@ -173,12 +164,6 @@ trait TLCDRRx{ this: TLCDRBase =>
rxFifo.io.enq.valid := CDRIn.io.axis.fire & rxCnt === 3.U
rxFifo.io.enq.bits := Cat( rxData(23, 0) , CDRIn.io.axis.bits.tdata )
// PriorityMux(Seq(
// (rxCnt === 0.U) -> Cat( CDRIn.io.axis.bits.tdata, 0.U(24.W) ),
// (rxCnt === 1.U) -> Cat( rxData(23,16), CDRIn.io.axis.bits.tdata, 0.U(16.W) ),
// (rxCnt === 2.U) -> Cat( rxData(23, 8), CDRIn.io.axis.bits.tdata, 0.U(8.W ) ),
// (rxCnt === 3.U) -> Cat( rxData(23, 0) , CDRIn.io.axis.bits.tdata ),
// ))
assert( ~(( CDRIn.io.axis.fire & CDRIn.io.axis.bits.tlast) & rxCnt =/= 3.U), "Assert Failed! Rx must 4-byte Align!" )
CDRIn.io.axis.ready := true.B
@@ -203,10 +188,6 @@ class TLCDR()(implicit p: Parameters) extends TLCDRBase() with TLCDRTx with TLCD
val isWriteTransDir = io.mem.fire & io.mem.addr(4,0) === "hc".U & io.mem.wstrb =/= 0.U
when( isWriteTransDir ){
dirSel := io.mem.wdata
}
@@ -215,8 +196,6 @@ class TLCDR()(implicit p: Parameters) extends TLCDRBase() with TLCDRTx with TLCD
( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready) |
( io.mem.wstrb === 0.U & Mux( io.mem.addr(4,0) === "h1c".U, rxFifo.io.deq.valid, true.B ) )
io.interrupt(0) := intTxEnd
io.interrupt(1) := intRxError
io.interrupt(2) := intRxStart
@@ -230,9 +209,6 @@ class TLCDR()(implicit p: Parameters) extends TLCDRBase() with TLCDRTx with TLCD
isTLReadRxFifo -> rxFifo.io.deq.bits
))
}