清理代码

src/main/scala/backBoard/ebus/CDRIn.scala

@@ -14,9 +14,6 @@ class CDRInIO extends Bundle{
 
 abstract class CDRInBase extends Module{
   def sampleRate: Int = 4
-  // require( sampleRate == 4 )
-
-  // require( (sampleRate % 2) == 1 )
 
   val io: CDRInIO = IO(new CDRInIO)
 
@@ -25,8 +22,6 @@ abstract class CDRInBase extends Module{
 
 trait CDRInOverSample{ this: CDRInBase =>
   val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
-  // val arbResult = VecInit(sampleReg).count( (x:Bool) => (x === true.B) ) > ((sampleRate-1) / 2).U
-
 
   val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) }
   val arbSel = Reg(UInt( log2Ceil(sampleRate).W ))
@@ -45,17 +40,6 @@ trait CDRInOverSample{ this: CDRInBase =>
     isArbLock := false.B
   }
 
-
-
-
-
-
-  // val arbResult = 
-  //   (sampleReg(3) & sampleReg(2) & sampleReg(1)) |
-  //   (sampleReg(3) & sampleReg(2) & sampleReg(0)) |
-  //   (sampleReg(3) & sampleReg(1) & sampleReg(0)) |
-  //   (sampleReg(2) & sampleReg(1) & sampleReg(0))
-
   val syncSerDat = ShiftRegister( 
     PriorityMux( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> sampleReg(i)) } )
     , 2 )