开放链路寄存器给spi访问读取

src/main/scala/backBoard/shin/Interface.scala

@@ -28,6 +28,7 @@ class CommonRegisterBundle extends Bundle{
   // val forwardByteCnt = UInt(32.W)
 
 
+
   // val wdtStatus   = UInt(16.W)
   // val wdtOverflow = UInt(8.W)
 
@@ -36,7 +37,6 @@ class CommonRegisterBundle extends Bundle{
 
   val syncPoint = UInt(64.W)
   val syncPeroid = UInt(32.W)
-  // val linkStatus = UInt(8.W)
 
 
   val smEnqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
@@ -96,8 +96,13 @@ class SlaveRegisterBundle extends Bundle{
   // val dcSyncWidth  = UInt(16.W)
 
 
-
+  //链路寄存器组
-
+  // val isDevOnLeft = UInt(2.W)
+  val isDevOnLeftModify = Bool()
+  val indexOfLeftDev = UInt(14.W)
+  val isDevOnRight = UInt(2.W)
+  val isDevOnRightModify = Bool()
+  val indexOfRightDev = UInt(14.W)
 
 
   // val downTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器 
@@ -163,6 +168,15 @@ class InterfaceIO extends Bundle{
   val mReg = Output(new MasterRegisterBundle)
   val sReg = Output(new SlaveRegisterBundle)
 
+  // val isDevOnLeft = Input(UInt(2.W))
+  val isDevOnLeftModify = Input(Bool())
+  val indexOfLeftDev = Input(UInt(14.W))
+
+  val isDevOnRight = Input(UInt(2.W))
+  val isDevOnRightModify = Input(Bool())
+  val indexOfRightDev = Input(UInt(14.W))
+
+
 
   // val smEnqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
   // val smDeqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
@@ -243,6 +257,14 @@ abstract class InterfaceBase extends Module{
         (addr === ("h80".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 )
       }) ++
 
+      Seq(
+        (addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, sReg.isDevOnLeftModify, 0.U(2.W) ),
+        (addr === "hc2".U ) -> sReg.indexOfRightDev(7,0),
+        (addr === "hc3".U ) -> sReg.indexOfRightDev(13,8),
+        (addr === "hc4".U ) -> sReg.indexOfLeftDev(7,0),
+        (addr === "hc5".U ) -> sReg.indexOfLeftDev(13,8),
+      ) ++
+
       Seq(
         //本地时钟
         (addr === "h100".U )  -> cReg.timeStamp(7,0),
@@ -705,7 +727,12 @@ with InterfaceSync
   // io.smEnqAddr := cReg.smEnqAddr
   // io.smDeqAddr := cReg.smDeqAddr
 
-
+  // sReg.isDevOnLeft        := io.isDevOnLeft
+  sReg.isDevOnLeftModify  := io.isDevOnLeftModify
+  sReg.indexOfLeftDev     := io.indexOfLeftDev
+  sReg.isDevOnRight       := io.isDevOnRight
+  sReg.isDevOnRightModify := io.isDevOnRightModify
+  sReg.indexOfRightDev    := io.indexOfRightDev
 
 
 

src/main/scala/backBoard/shin/ShinTop.scala

@@ -346,6 +346,14 @@ trait ShinTopSlave{ this: ShinTopBase =>
   }
 
   interface.io.lvds <> slaveParser.io.lvds
+
+  //从站链路寄存器
+  // interface.io.isDevOnLeft := slaveParser.io.isDevOnLeft
+  interface.io.isDevOnLeftModify := slaveParser.io.isDevOnLeftModify
+  interface.io.indexOfLeftDev := slaveParser.io.indexOfLeftDev
+  interface.io.isDevOnRight := slaveParser.io.isDevOnRight
+  interface.io.isDevOnRightModify := slaveParser.io.isDevOnRightModify
+  interface.io.indexOfRightDev := slaveParser.io.indexOfRightDev
 }
 
 

src/main/scala/backBoard/shin/SlaveParser.scala

@@ -46,6 +46,15 @@ class SlaveParserIO extends Bundle{
 
   val trigAddr = Input( Vec(8, UInt(15.W)) )
 
+  //开放链路寄存器组给interface
+  // val isDevOnLeft        = Output(UInt(2.W))
+  val isDevOnLeftModify  = Output(Bool())
+  val indexOfLeftDev     = Output(UInt(14.W))
+  val isDevOnRight       = Output(UInt(2.W))
+  val isDevOnRightModify = Output(Bool())
+  val indexOfRightDev    = Output(UInt(14.W))
+
+
   val mstDeltaTimeStamp = Output(UInt(32.W))
   val slvDeltaTime = Output(UInt(32.W))
   val deltaFinal        = Output(UInt(32.W))
@@ -84,10 +93,18 @@ abstract class SlaveParserBase extends Module{
   val isReadyToProbe  = RegInit(false.B)
   val isAckProbe = RegInit(false.B)
   val isLastDevice: Bool = RegInit(true.B)
-  val isDeviceModified: Bool = RegInit(true.B)
+
+  // val isDevOnLeft        = RegInit(0.U(2.W));  io.isDevOnLeft        := isDevOnLeft
+  val isDevOnLeftModify  = RegInit(false.B);   io.isDevOnLeftModify  := isDevOnLeftModify
+  val indexOfLeftDev     = RegInit(0.U(14.W)); io.indexOfLeftDev     := indexOfLeftDev
+  io.isDevOnRight       := Mux( isLastDevice, "b01".U, "b10".U )
+  val isDevOnRightModify = RegInit(false.B);   io.isDevOnRightModify := isDevOnRightModify
+  val indexOfRightDev    = RegInit(0.U(14.W)); io.indexOfRightDev    := indexOfRightDev
+
+  // val isDeviceModified: Bool = RegInit(true.B)
 
   val localDevIndex = RegInit(0.U(14.W)) //当前设备索引
-  dontTouch(localDevIndex)
+  // dontTouch(localDevIndex)
 
 
 
@@ -354,7 +371,10 @@ trait SlaveParserIndex{ this: SlaveParserBase =>
         downRecParser.io.subMsgReq.bits.style === 0.U &
         downRecParser.io.subMsgReq.bits.operator === "hd".U ){ //设置顺序地址
     localDevIndex := downRecParser.io.subMsgReq.bits.workCnt + 1.U
-    isDeviceModified := false.B
+    isDevOnLeftModify  := false.B
+    indexOfLeftDev     := downRecParser.io.subMsgReq.bits.workCnt
+
+    isDevOnRightModify := false.B
     when( isDownRecPing ){
       downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
     } .otherwise{ //pong
@@ -689,12 +709,23 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
   }
 
 
-  when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
+
-    when( upRecParser.io.frameReq.bits.frameInfo =/= localDevIndex + 1.U ){ //索引不对
+
-      isDeviceModified := true.B
+
+
+  when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //下行来了一个嗅探包
+    when( downRecParser.io.frameReq.bits.frameInfo =/= localDevIndex - 1.U ){ //索引不对
+      isDevOnLeftModify := true.B
+      indexOfLeftDev := downRecParser.io.frameReq.bits.frameInfo
     }
   }
 
+  when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
+    when( upRecParser.io.frameReq.bits.frameInfo =/= localDevIndex + 1.U ){ //索引不对
+      isDevOnRightModify := true.B
+      indexOfRightDev := upRecParser.io.frameReq.bits.frameInfo
+    }
+  }