开放链路寄存器给spi访问读取

src/main/scala/backBoard/shin/Interface.scala

@@ -28,6 +28,7 @@ class CommonRegisterBundle extends Bundle{
   // val forwardByteCnt = UInt(32.W)
 
 
+
   // val wdtStatus   = UInt(16.W)
   // val wdtOverflow = UInt(8.W)
 
@@ -36,7 +37,6 @@ class CommonRegisterBundle extends Bundle{
 
   val syncPoint = UInt(64.W)
   val syncPeroid = UInt(32.W)
-  // val linkStatus = UInt(8.W)
 
 
   val smEnqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
@@ -96,8 +96,13 @@ class SlaveRegisterBundle extends Bundle{
   // val dcSyncWidth  = UInt(16.W)
 
 
-
-
+  //链路寄存器组
+  // val isDevOnLeft = UInt(2.W)
+  val isDevOnLeftModify = Bool()
+  val indexOfLeftDev = UInt(14.W)
+  val isDevOnRight = UInt(2.W)
+  val isDevOnRightModify = Bool()
+  val indexOfRightDev = UInt(14.W)
 
 
   // val downTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器 
@@ -163,6 +168,15 @@ class InterfaceIO extends Bundle{
   val mReg = Output(new MasterRegisterBundle)
   val sReg = Output(new SlaveRegisterBundle)
 
+  // val isDevOnLeft = Input(UInt(2.W))
+  val isDevOnLeftModify = Input(Bool())
+  val indexOfLeftDev = Input(UInt(14.W))
+
+  val isDevOnRight = Input(UInt(2.W))
+  val isDevOnRightModify = Input(Bool())
+  val indexOfRightDev = Input(UInt(14.W))
+
+
 
   // val smEnqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
   // val smDeqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
@@ -243,6 +257,14 @@ abstract class InterfaceBase extends Module{
         (addr === ("h80".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 )
       }) ++
 
+      Seq(
+        (addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, sReg.isDevOnLeftModify, 0.U(2.W) ),
+        (addr === "hc2".U ) -> sReg.indexOfRightDev(7,0),
+        (addr === "hc3".U ) -> sReg.indexOfRightDev(13,8),
+        (addr === "hc4".U ) -> sReg.indexOfLeftDev(7,0),
+        (addr === "hc5".U ) -> sReg.indexOfLeftDev(13,8),
+      ) ++
+
       Seq(
         //本地时钟
         (addr === "h100".U )  -> cReg.timeStamp(7,0),
@@ -705,7 +727,12 @@ with InterfaceSync
   // io.smEnqAddr := cReg.smEnqAddr
   // io.smDeqAddr := cReg.smDeqAddr
 
-
+  // sReg.isDevOnLeft        := io.isDevOnLeft
+  sReg.isDevOnLeftModify  := io.isDevOnLeftModify
+  sReg.indexOfLeftDev     := io.indexOfLeftDev
+  sReg.isDevOnRight       := io.isDevOnRight
+  sReg.isDevOnRightModify := io.isDevOnRightModify
+  sReg.indexOfRightDev    := io.indexOfRightDev