compile tilelink

src/main/scala/mac/MAC.scala

@@ -9,6 +9,18 @@ import freechips.rocketchip.tilelink._
 
 class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
 
+val tlClientParameters = TLMasterPortParameters.v1(
+    Seq(TLMasterParameters.v1(
+      name = "tlSlvIO",
+      sourceId = IdRange(0, 1),
+    ))
+  )
+
+  val tlClientIONode = 
+    if(!isTileLink){ None } else {
+      Some(TLClientNode(Seq(tlClientParameters)))
+    }
+
   val tlMasterNode = 
     if(!isTileLink){ None } else {
       Some(    
@@ -25,6 +37,15 @@ class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
       )
     }
 
+  if( !isTileLink ){} else {
+    tlMasterNode.get := tlClientIONode.get
+
+    val tlSlv = InModuleBody {
+      tlClientIONode.get.makeIOs()
+    }
+  }
+
+
 
   lazy val module = new MacImp(this)
 
@@ -38,7 +59,7 @@ class MacIO(implicit p: Parameters) extends MacBundle{
   // def isTileLink = false
 
   val wbSlv = if( !isTileLink ) { Some(new MacWishboneSlaveIO)  } else {None}
-  val wbMst = if( !isTileLink ) { Some(new MacWishboneMasterIO) } else {None}
+  val wbMst = if( true ) { Some(new MacWishboneMasterIO) } else {None}
 
   // Tx
   val mtx_clk_pad_i = Input(Bool())
@@ -64,6 +85,9 @@ class MacImp(outer: Mac)(implicit p: Parameters) extends LazyModuleImp(outer) wi
   val io = IO(new MacIO with MDIO)
   val ( slv_bus, slv_edge ) = (if(!isTileLink) {(None, None)} else {(Some(outer.tlMasterNode.get.in.head._1), Some(outer.tlMasterNode.get.in.head._2))} )
   
+
+
+
 val r_ClkDiv            = Wire(UInt(8.W))
 val r_MiiNoPre          = Wire(Bool())
 val r_CtrlData          = Wire(UInt(16.W))
@@ -304,9 +328,17 @@ dontTouch(RegCs                      )
 
 val ethReg = Module(new MacReg)
 
-ethReg.io.DataIn              := io.wbSlv.get.WB_DAT_I
+if( !isTileLink ){
-ethReg.io.Address             := io.wbSlv.get.WB_ADR_I(9,2)
+  ethReg.io.DataIn              := io.wbSlv.get.WB_DAT_I
-ethReg.io.Rw                  := io.wbSlv.get.WB_WE_I
+  ethReg.io.Address             := io.wbSlv.get.WB_ADR_I(9,2)
+  ethReg.io.Rw                  := io.wbSlv.get.WB_WE_I  
+} else{
+  ethReg.io.DataIn              := slv_bus.get.a.bits.data
+  ethReg.io.Address             := slv_bus.get.a.bits.address(9,2)
+  ethReg.io.Rw                  := slv_bus.get.a.bits.opcode === 0.U | slv_bus.get.a.bits.opcode === 1.U
+}
+
+
 ethReg.io.Cs                  := RegCs
 ethReg.io.WCtrlDataStart      := WCtrlDataStart
 ethReg.io.RStatStart          := RStatStart
@@ -668,7 +700,7 @@ val rxethmac = Module(new MacRx)
 
 
   val wishbone = Module(new MacTileLink(slv_edge))
-
+  if( !isTileLink ){
     wishbone.io.wbSlv.get.WB_DAT_I := io.wbSlv.get.WB_DAT_I
     io.wbSlv.get.WB_DAT_O := wishbone.io.wbSlv.get.WB_DAT_O
     wishbone.io.wbSlv.get.WB_ADR_I := io.wbSlv.get.WB_ADR_I
@@ -678,6 +710,18 @@ val rxethmac = Module(new MacRx)
     wishbone.io.wbSlv.get.WB_STB_I := io.wbSlv.get.WB_STB_I
     io.wbSlv.get.WB_ACK_O := wishbone.io.wbSlv.get.WB_ACK_O
     io.wbSlv.get.WB_ERR_O := wishbone.io.wbSlv.get.WB_ERR_O
+  } else {
+
+    wishbone.io.tlSlv.get.A.valid := slv_bus.get.a.valid 
+    wishbone.io.tlSlv.get.A.bits  := slv_bus.get.a.bits 
+    slv_bus.get.a.ready := wishbone.io.tlSlv.get.A.ready
+
+    slv_bus.get.d.valid := wishbone.io.tlSlv.get.D.valid
+    slv_bus.get.d.bits  := wishbone.io.tlSlv.get.D.bits
+    wishbone.io.tlSlv.get.D.ready := slv_bus.get.d.ready
+
+  }
+
 
 
   io.wbMst.get.m_wb_adr_o := wishbone.io.wbMst.get.m_wb_adr_o
@@ -802,4 +846,6 @@ val rxethmac = Module(new MacRx)
   CarrierSenseLost     := macstatus.io.CarrierSenseLost
   LatchedMRxErr        := macstatus.io.LatchedMRxErr
 
+
+
 }

src/main/scala/mac/MacTilelink.scala

@@ -27,7 +27,7 @@ abstract class MacTileLinkBase(edge: Option[TLEdgeIn])(implicit p: Parameters) e
     val wbSlv = if( !isTileLink ) { Some(new MacWishboneSlaveIO) } else {None}
     val tlSlv = if(  isTileLink ) { Some(new MacTileLinkSlaveIO) } else {None}
 
-    val wbMst = if( !isTileLink ) { Some(new MacWishboneMasterIO) } else {None}
+    val wbMst = if( true ) { Some(new MacWishboneMasterIO) } else {None}
 
     // Rx Status signals
     val InvalidSymbol   = Input(Bool())             // Invalid symbol was received during reception in 100 Mbps mode
@@ -395,7 +395,7 @@ abstract class MacTileLinkBase(edge: Option[TLEdgeIn])(implicit p: Parameters) e
     // BDRead   := BDCs.orR & ~io.wbSlv.get.WB_WE_I
 
     ram_addr := (if( !isTileLink ) {io.wbSlv.get.WB_ADR_I(9,2)}          else {io.tlSlv.get.A.bits.address(9,2)}) //[11:2 ] ->[9:2]
-    ram_di   := (if( !isTileLink ) {io.wbSlv.get.WB_DAT_I} else { io.tlSlv.get.A.bits.data })
+    ram_di   := (if( !isTileLink ) {io.wbSlv.get.WB_DAT_I}               else {io.tlSlv.get.A.bits.data })
     BDWrite  := (if( !isTileLink ) {BDCs & Fill(4,io.wbSlv.get.WB_WE_I)} else {BDCs & Fill(4,(io.tlSlv.get.A.bits.opcode === 0.U) || (io.tlSlv.get.A.bits.opcode === 1.U))} )
     BDRead   := (if( !isTileLink ) {BDCs.orR & ~io.wbSlv.get.WB_WE_I}    else {BDCs.orR & (io.tlSlv.get.A.bits.opcode === 4.U)})
   } .elsewhen( RAMAccessEnable === BitPat("b10000") ){
@@ -1139,19 +1139,21 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, (ReadTxDataFromMemory & ~BlockRead
     io.wbSlv.get.WB_ERR_O := RegNext(io.wbSlv.get.WB_STB_I & io.wbSlv.get.WB_CYC_I & (~(io.wbSlv.get.WB_SEL_I.orR) | CsMiss) & ~io.wbSlv.get.WB_ERR_O, false.B)
 
   } else {
-    io.RegCs := Fill(4, io.tlSlv.get.A.fire & io.tlSlv.get.A.bits.mask.orR & ~io.tlSlv.get.A.bits.address(11) & ~io.tlSlv.get.A.bits.address(10)) & io.tlSlv.get.A.bits.mask // 0x0   - 0x3FF
+    io.RegCs := Fill(4, io.tlSlv.get.A.valid & io.tlSlv.get.A.bits.mask.orR & ~io.tlSlv.get.A.bits.address(11) & ~io.tlSlv.get.A.bits.address(10)) & io.tlSlv.get.A.bits.mask // 0x0   - 0x3FF
-       BDCs  := Fill(4, io.tlSlv.get.A.fire & io.tlSlv.get.A.bits.mask.orR & ~io.tlSlv.get.A.bits.address(11) &  io.tlSlv.get.A.bits.address(10)) & io.tlSlv.get.A.bits.mask // 0x400 - 0x7FF
+       BDCs  := Fill(4, io.tlSlv.get.A.valid & io.tlSlv.get.A.bits.mask.orR & ~io.tlSlv.get.A.bits.address(11) &  io.tlSlv.get.A.bits.address(10)) & io.tlSlv.get.A.bits.mask // 0x400 - 0x7FF
-      CsMiss :=         io.tlSlv.get.A.fire & io.tlSlv.get.A.bits.mask.orR &  io.tlSlv.get.A.bits.address(11)    // 0x800 - 0xfFF     // When access to the address between 0x800 and 0xfff occurs, acknowledge is set but data is not valid.
+      CsMiss :=         io.tlSlv.get.A.valid & io.tlSlv.get.A.bits.mask.orR &  io.tlSlv.get.A.bits.address(11)    // 0x800 - 0xfFF     // When access to the address between 0x800 and 0xfff occurs, acknowledge is set but data is not valid.
     
     val slvAInfo = RegEnable( io.tlSlv.get.A.bits, io.tlSlv.get.A.fire )
     val slvDValid = RegInit(false.B); io.tlSlv.get.D.valid := slvDValid
     val slvDDat = Reg(UInt(32.W))
 
+
+
     when( io.tlSlv.get.D.fire ){
       slvDValid := false.B
-    } .elsewhen(io.RegCs.orR | BDAck){
+    } .elsewhen(io.tlSlv.get.A.fire){
       slvDValid := true.B
-      slvDDat := Mux( ((io.RegCs.orR) & ~io.wbSlv.get.WB_WE_I), io.RegDataOut, BD_WB_DAT_O )
+      slvDDat := Mux( ((io.RegCs.orR) & io.tlSlv.get.A.bits.opcode === 4.U), io.RegDataOut, BD_WB_DAT_O )
     }
 
     when(slvAInfo.opcode === 4.U) {
@@ -1160,7 +1162,12 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, (ReadTxDataFromMemory & ~BlockRead
       io.tlSlv.get.D.bits := edge.get.AccessAck(slvAInfo)
     }
 
-    when( io.tlSlv.get.A.fire & (~(io.wbSlv.get.WB_SEL_I.orR) | CsMiss) ){
+
+
+    io.tlSlv.get.A.ready := RegNext(io.RegCs.orR, false.B) | BDAck
+    assert( ~(io.tlSlv.get.A.ready & ~io.tlSlv.get.A.valid) )
+
+    when( io.tlSlv.get.A.fire & (~(io.tlSlv.get.A.bits.mask.orR) | CsMiss) ){
       assert( false.B, "Assert Failed, tileLink access an undefine region!" )
     }
   }

src/main/scala/mac/Parameters.scala

@@ -14,7 +14,7 @@ case object MacParamsKey extends Field[MacSetting]
 
 
 case class MacSetting(
-  isTileLink: Boolean = false
+  isTileLink: Boolean = true
 ){
 
 }