ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

opt

Browse Source
This commit is contained in:
RuigeLee
2023-06-29 21:14:51 +08:00
parent 61e36c59d8
commit 59a2f2e054
1 changed files with 72 additions and 189 deletions
Download Patch File Download Diff File Expand all files Collapse all files

261
src/main/scala/mac/MacTilelink.scala
View File

@@ -1190,8 +1190,8 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDat
val Busy_IRQ_sync1 = RegNext(Busy_IRQ_rck_rxclk) val Busy_IRQ_sync1 = RegNext(Busy_IRQ_rck_rxclk)
val Busy_IRQ_sync2 = RegNext(Busy_IRQ_sync1) val Busy_IRQ_sync2 = RegNext(Busy_IRQ_sync1)
val Busy_IRQ_sync3 = RegNext(Busy_IRQ_sync2) val Busy_IRQ_sync3 = RegNext(Busy_IRQ_sync2)
val Busy_IRQ_syncb1 = Reg(Bool()) val Busy_IRQ_syncb1 = RegNext(Busy_IRQ_sync2, false.B)
val Busy_IRQ_syncb2 = Reg(Bool()) val Busy_IRQ_syncb2 = RegNext(Busy_IRQ_syncb1, false.B)
@@ -1226,89 +1226,55 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDat
trait MacTileLinkTXClk{ this: MacTileLinkBase => trait MacTileLinkTXClk{ this: MacTileLinkBase =>
withClockAndReset( io.MTxClk.asClock, reset ) { withClockAndReset( io.MTxClk.asClock, reset ) {
val Flop = Reg(Bool()) val Flop = RegInit(false.B)
val BlockingTxStatusWrite_sync1 = Reg(Bool()) // Synchronizing BlockingTxStatusWrite to MTxClk
val BlockingTxStatusWrite_sync2 = Reg(Bool()); BlockingTxStatusWrite_sync2_txclk := BlockingTxStatusWrite_sync2 val BlockingTxStatusWrite_sync1 = RegNext(BlockingTxStatusWrite, false.B)
val BlockingTxStatusWrite_sync3 = Reg(Bool()); BlockingTxStatusWrite_sync3_txclk := BlockingTxStatusWrite_sync3 val BlockingTxStatusWrite_sync2 = RegNext(BlockingTxStatusWrite_sync1, false.B); BlockingTxStatusWrite_sync2_txclk := BlockingTxStatusWrite_sync2
val TxStartFrm_sync1 = Reg(Bool()) val BlockingTxStatusWrite_sync3 = RegNext(BlockingTxStatusWrite_sync2, false.B); BlockingTxStatusWrite_sync3_txclk := BlockingTxStatusWrite_sync3
val TxStartFrm_sync2 = Reg(Bool()); TxStartFrm_sync2_txclk := TxStartFrm_sync2 // Synchronizing TxStartFrm_wb to MTxClk
val TxStartFrm = Reg(Bool()); io.TxStartFrm := TxStartFrm val TxStartFrm_sync1 = RegNext( TxStartFrm_wb, false.B)
val TxEndFrm = Reg(Bool()); io.TxEndFrm := TxEndFrm val TxStartFrm_sync2 = RegNext( TxStartFrm_sync1, false.B); TxStartFrm_sync2_txclk := TxStartFrm_sync2
val TxData = Reg(UInt(8.W)); io.TxData := TxData val TxStartFrm = RegInit(false.B); io.TxStartFrm := TxStartFrm
val TxUnderRun = Reg(Bool()); io.TxUnderRun := TxUnderRun val TxEndFrm = RegInit(false.B); io.TxEndFrm := TxEndFrm
val TxDataLatched = Reg(UInt(32.W)) val TxData = RegInit(0.U(8.W)); io.TxData := TxData
val TxByteCnt = Reg(UInt(2.W)) val TxUnderRun = RegInit(false.B); io.TxUnderRun := TxUnderRun
val LastWord = Reg(Bool()) val TxDataLatched = RegInit(0.U(32.W))
val ReadTxDataFromFifo_tck = Reg(Bool()); ReadTxDataFromFifo_tck_txclk := ReadTxDataFromFifo_tck val TxByteCnt = RegInit(0.U(2.W))
val TxAbort_q = Reg(Bool()) val LastWord = RegInit(false.B)
val TxRetry_q = Reg(Bool()) val ReadTxDataFromFifo_tck = RegInit(false.B); ReadTxDataFromFifo_tck_txclk := ReadTxDataFromFifo_tck
val TxUsedData_q = Reg(Bool())
val ReadTxDataFromFifo_syncb1 = Reg(Bool()) // Generating delayed signals
val ReadTxDataFromFifo_syncb2 = Reg(Bool()) val TxAbort_q = RegNext( io.TxAbort, false.B)
val ReadTxDataFromFifo_syncb3 = Reg(Bool()) val TxRetry_q = RegNext( io.TxRetry, false.B)
val TxUsedData_q = RegNext( io.TxUsedData, false.B)
val ReadTxDataFromFifo_syncb1 = RegNext( ReadTxDataFromFifo_sync2, false.B)
val ReadTxDataFromFifo_syncb2 = RegNext( ReadTxDataFromFifo_syncb1, false.B)
val ReadTxDataFromFifo_syncb3 = RegNext( ReadTxDataFromFifo_syncb2, false.B)
// Changes for tx occur every second clock. Flop is used for this manner. // Changes for tx occur every second clock. Flop is used for this manner.
when(reset.asBool){ when( io.TxDone | io.TxAbort | TxRetry_q){
Flop := false.B
} .elsewhen( io.TxDone | io.TxAbort | TxRetry_q){
Flop := false.B Flop := false.B
} .elsewhen ( io.TxUsedData ){ } .elsewhen ( io.TxUsedData ){
Flop := ~Flop Flop := ~Flop
} }
// Synchronizing BlockingTxStatusWrite to MTxClk when(TxStartFrm_sync2){
when(reset.asBool){
BlockingTxStatusWrite_sync1 := false.B
BlockingTxStatusWrite_sync2 := false.B
BlockingTxStatusWrite_sync3 := false.B
} .otherwise{
BlockingTxStatusWrite_sync1 := BlockingTxStatusWrite;
BlockingTxStatusWrite_sync2 := BlockingTxStatusWrite_sync1;
BlockingTxStatusWrite_sync3 := BlockingTxStatusWrite_sync2;
}
// Synchronizing TxStartFrm_wb to MTxClk
when(reset.asBool){
TxStartFrm_sync1 := false.B
TxStartFrm_sync2 := false.B
} .otherwise{
TxStartFrm_sync1 := TxStartFrm_wb
TxStartFrm_sync2 := TxStartFrm_sync1;
}
when(reset.asBool){
TxStartFrm := false.B
} .elsewhen(TxStartFrm_sync2){
TxStartFrm := true.B TxStartFrm := true.B
} .elsewhen(TxUsedData_q | ~TxStartFrm_sync2 & (io.TxRetry & (~TxRetry_q) | io.TxAbort & (~TxAbort_q))){ } .elsewhen(TxUsedData_q | ~TxStartFrm_sync2 & (io.TxRetry & (~TxRetry_q) | io.TxAbort & (~TxAbort_q))){
TxStartFrm := false.B TxStartFrm := false.B
} }
// Generating delayed signals
when(reset.asBool){
TxAbort_q := false.B
TxRetry_q := false.B
TxUsedData_q := false.B
} .otherwise{
TxAbort_q := io.TxAbort
TxRetry_q := io.TxRetry
TxUsedData_q := io.TxUsedData
}
// Indication of the last word // Indication of the last word
when(reset.asBool){ when( (TxEndFrm | io.TxAbort | io.TxRetry) & Flop ){
LastWord := false.B
} .elsewhen( (TxEndFrm | io.TxAbort | io.TxRetry) & Flop ){
LastWord := false.B LastWord := false.B
} .elsewhen( io.TxUsedData & Flop & TxByteCnt === 3.U ){ } .elsewhen( io.TxUsedData & Flop & TxByteCnt === 3.U ){
LastWord := TxEndFrm_wb LastWord := TxEndFrm_wb
} }
// Tx end frame generation // Tx end frame generation
when(reset.asBool){ when(Flop & TxEndFrm | io.TxAbort | TxRetry_q){
TxEndFrm := false.B
} .elsewhen(Flop & TxEndFrm | io.TxAbort | TxRetry_q){
TxEndFrm := false.B TxEndFrm := false.B
} .elsewhen(Flop & LastWord){ } .elsewhen(Flop & LastWord){
TxEndFrm := TxEndFrm :=
@@ -1323,9 +1289,7 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
// Tx data selection (latching) // Tx data selection (latching)
when(reset.asBool){ when( TxStartFrm_sync2 & ~TxStartFrm ){
TxData := 0.U
} .elsewhen( TxStartFrm_sync2 & ~TxStartFrm ){
TxData := Mux1H(Seq( TxData := Mux1H(Seq(
( TxPointerLSB === 0.U ) -> TxData_wb(31,24),// Big Endian Byte Ordering ( TxPointerLSB === 0.U ) -> TxData_wb(31,24),// Big Endian Byte Ordering
( TxPointerLSB === 1.U ) -> TxData_wb(23,16),// Big Endian Byte Ordering ( TxPointerLSB === 1.U ) -> TxData_wb(23,16),// Big Endian Byte Ordering
@@ -1346,9 +1310,7 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
// Latching tx data // Latching tx data
when(reset.asBool){ when(
TxDataLatched := 0.U
} .elsewhen(
TxStartFrm_sync2 & ~TxStartFrm | TxStartFrm_sync2 & ~TxStartFrm |
io.TxUsedData & Flop & TxByteCnt === 3.U | io.TxUsedData & Flop & TxByteCnt === 3.U |
TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U){ TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U){
@@ -1356,12 +1318,10 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
} }
val TxUnderRun_sync1 = Reg(Bool()) val TxUnderRun_sync1 = RegInit(false.B)
// Tx under run // Tx under run
when(reset.asBool){ when(TxUnderRun_wb){
TxUnderRun_sync1 := false.B
} .elsewhen(TxUnderRun_wb){
TxUnderRun_sync1 := true.B TxUnderRun_sync1 := true.B
} .elsewhen(BlockingTxStatusWrite_sync2){ } .elsewhen(BlockingTxStatusWrite_sync2){
TxUnderRun_sync1 := false.B TxUnderRun_sync1 := false.B
@@ -1369,9 +1329,7 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
// Tx under run // Tx under run
when(reset.asBool){ when(BlockingTxStatusWrite_sync2){
TxUnderRun := false.B
} .elsewhen(BlockingTxStatusWrite_sync2){
TxUnderRun := false.B TxUnderRun := false.B
} .elsewhen(TxUnderRun_sync1){ } .elsewhen(TxUnderRun_sync1){
TxUnderRun := true.B TxUnderRun := true.B
@@ -1380,9 +1338,7 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
// Tx Byte counter // Tx Byte counter
when(reset.asBool){ when(TxAbort_q | TxRetry_q){
TxByteCnt := 0.U
} .elsewhen(TxAbort_q | TxRetry_q){
TxByteCnt := 0.U TxByteCnt := 0.U
} .elsewhen(TxStartFrm & ~io.TxUsedData){ } .elsewhen(TxStartFrm & ~io.TxUsedData){
TxByteCnt := Mux1H(Seq( TxByteCnt := Mux1H(Seq(
@@ -1395,27 +1351,13 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
TxByteCnt := TxByteCnt + 1.U TxByteCnt := TxByteCnt + 1.U
} }
when(reset.asBool){ when(TxStartFrm_sync2 & ~TxStartFrm | io.TxUsedData & Flop & TxByteCnt === 3.U &
ReadTxDataFromFifo_tck := false.B
} .elsewhen(TxStartFrm_sync2 & ~TxStartFrm | io.TxUsedData & Flop & TxByteCnt === 3.U &
~LastWord | TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U ){ ~LastWord | TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U ){
ReadTxDataFromFifo_tck := true.B ReadTxDataFromFifo_tck := true.B
} .elsewhen(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3){ } .elsewhen(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3){
ReadTxDataFromFifo_tck := false.B ReadTxDataFromFifo_tck := false.B
} }
when(reset.asBool){
ReadTxDataFromFifo_syncb1 := false.B
ReadTxDataFromFifo_syncb2 := false.B
ReadTxDataFromFifo_syncb3 := false.B
}.otherwise{
ReadTxDataFromFifo_syncb1 := ReadTxDataFromFifo_sync2;
ReadTxDataFromFifo_syncb2 := ReadTxDataFromFifo_syncb1;
ReadTxDataFromFifo_syncb3 := ReadTxDataFromFifo_syncb2;
}
} }
} }
@@ -1459,48 +1401,42 @@ trait MacTileLinkRXClk{ this: MacTileLinkBase =>
withClockAndReset( io.MRxClk.asClock, reset ){ withClockAndReset( io.MRxClk.asClock, reset ){
val RxDataLatched2 = Reg(UInt(32.W)); RxDataLatched2_rxclk := RxDataLatched2 val RxDataLatched2 = RegInit(0.U(32.W)); RxDataLatched2_rxclk := RxDataLatched2
val RxDataLatched1 = Reg(UInt(24.W)) // Big Endian Byte Ordering[31:8] val RxDataLatched1 = RegInit(0.U(24.W)) // Big Endian Byte Ordering[31:8]
val RxValidBytes = Reg(UInt(2.W)) val RxValidBytes = RegInit(1.U(2.W))
val RxByteCnt = Reg(UInt(2.W)); RxByteCnt_rxclk := RxByteCnt val RxByteCnt = RegInit(0.U(2.W)); RxByteCnt_rxclk := RxByteCnt
val LastByteIn = Reg(Bool()); LastByteIn_rxclk := LastByteIn val LastByteIn = RegInit(false.B); LastByteIn_rxclk := LastByteIn
val ShiftWillEnd = Reg(Bool()); ShiftWillEnd_rxclk := ShiftWillEnd val ShiftWillEnd = RegInit(false.B); ShiftWillEnd_rxclk := ShiftWillEnd
val WriteRxDataToFifo = Reg(Bool()); WriteRxDataToFifo_rxclk := WriteRxDataToFifo val WriteRxDataToFifo = RegInit(false.B); WriteRxDataToFifo_rxclk := WriteRxDataToFifo
val LatchedRxLength = Reg(UInt(16.W)); LatchedRxLength_rxclk := LatchedRxLength val LatchedRxLength = RegInit(0.U(16.W)); LatchedRxLength_rxclk := LatchedRxLength
val RxAbortLatched = Reg(Bool()); RxAbortLatched_rxclk := RxAbortLatched val RxAbortLatched = RegInit(false.B); RxAbortLatched_rxclk := RxAbortLatched
val RxStatusInLatched = Reg(UInt(9.W)); RxStatusInLatched_rxclk := RxStatusInLatched val RxStatusInLatched = RegInit(0.U(9.W)); RxStatusInLatched_rxclk := RxStatusInLatched
val ShiftEnded_rck = Reg(Bool()); ShiftEnded_rck_txclk := ShiftEnded_rck val ShiftEnded_rck = RegInit(false.B); ShiftEnded_rck_txclk := ShiftEnded_rck
val ShiftEndedSync_c1 = Reg(Bool()) val ShiftEndedSync_c1 = RegNext( ShiftEndedSync2, false.B)
val ShiftEndedSync_c2 = Reg(Bool()) val ShiftEndedSync_c2 = RegNext( ShiftEndedSync_c1, false.B)
val RxAbortSyncb1 = Reg(Bool()) val RxAbortSyncb1 = RegNext( RxAbortSync2, false.B)
val RxAbortSyncb2 = Reg(Bool()) val RxAbortSyncb2 = RegNext( RxAbortSyncb1, false.B)
val RxEnableWindow = Reg(Bool()); RxEnableWindow_rxclk := RxEnableWindow val RxEnableWindow = RegInit(false.B); RxEnableWindow_rxclk := RxEnableWindow
val LatchedRxStartFrm = Reg(Bool()); LatchedRxStartFrm_rxclk := LatchedRxStartFrm val LatchedRxStartFrm = RegInit(false.B); LatchedRxStartFrm_rxclk := LatchedRxStartFrm
val RxStatusWriteLatched_sync1 = Reg(Bool()) val RxStatusWriteLatched_sync1 = RegNext(RxStatusWriteLatched, false.B)
val RxStatusWriteLatched_sync2 = Reg(Bool()); io.RxStatusWriteLatched_sync2 := RxStatusWriteLatched_sync2 val RxStatusWriteLatched_sync2 = RegNext(RxStatusWriteLatched_sync1, false.B); io.RxStatusWriteLatched_sync2 := RxStatusWriteLatched_sync2
// Indicating that last byte is being reveived // Indicating that last byte is being reveived
when(reset.asBool){ when(ShiftWillEnd & RxByteCnt.andR | io.RxAbort){
LastByteIn := false.B
} .elsewhen(ShiftWillEnd & RxByteCnt.andR | io.RxAbort){
LastByteIn := false.B LastByteIn := false.B
} .elsewhen(io.RxValid & RxReady & io.RxEndFrm & ~(RxByteCnt.andR) & RxEnableWindow){ } .elsewhen(io.RxValid & RxReady & io.RxEndFrm & ~(RxByteCnt.andR) & RxEnableWindow){
LastByteIn := true.B LastByteIn := true.B
} }
// Indicating that data reception will end // Indicating that data reception will end
when(reset.asBool){ when(ShiftEnded_rck | io.RxAbort){
ShiftWillEnd := false.B
} .elsewhen(ShiftEnded_rck | io.RxAbort){
ShiftWillEnd := false.B ShiftWillEnd := false.B
} .elsewhen(StartShiftWillEnd){ } .elsewhen(StartShiftWillEnd){
ShiftWillEnd := true.B ShiftWillEnd := true.B
} }
// Receive byte counter // Receive byte counter
when(reset.asBool){ when(ShiftEnded_rck | io.RxAbort){
RxByteCnt := 0.U
} .elsewhen(ShiftEnded_rck | io.RxAbort){
RxByteCnt := 0.U RxByteCnt := 0.U
} .elsewhen(io.RxValid & io.RxStartFrm & RxReady){ } .elsewhen(io.RxValid & io.RxStartFrm & RxReady){
RxByteCnt := Mux1H(Seq( RxByteCnt := Mux1H(Seq(
@@ -1514,9 +1450,7 @@ trait MacTileLinkRXClk{ this: MacTileLinkBase =>
} }
// Indicates how many bytes are valid within the last word // Indicates how many bytes are valid within the last word
when(reset.asBool){ when(io.RxValid & io.RxStartFrm){
RxValidBytes := 1.U
} .elsewhen(io.RxValid & io.RxStartFrm){
RxValidBytes := Mux1H(Seq( RxValidBytes := Mux1H(Seq(
( RxPointerLSB_rst === 0.U ) -> 1.U, ( RxPointerLSB_rst === 0.U ) -> 1.U,
( RxPointerLSB_rst === 1.U ) -> 2.U, ( RxPointerLSB_rst === 1.U ) -> 2.U,
@@ -1527,9 +1461,7 @@ trait MacTileLinkRXClk{ this: MacTileLinkBase =>
RxValidBytes := RxValidBytes + 1.U RxValidBytes := RxValidBytes + 1.U
} }
when(reset.asBool){ when(io.RxValid & RxReady & ~LastByteIn){
RxDataLatched1 := 0.U
} .elsewhen(io.RxValid & RxReady & ~LastByteIn){
when(io.RxStartFrm){ when(io.RxStartFrm){
RxDataLatched1 := Mux1H(Seq( RxDataLatched1 := Mux1H(Seq(
( RxPointerLSB_rst === 0.U ) -> Cat( io.RxData, RxDataLatched1(15,0)),// Big Endian Byte Ordering ( RxPointerLSB_rst === 0.U ) -> Cat( io.RxData, RxDataLatched1(15,0)),// Big Endian Byte Ordering
@@ -1549,9 +1481,7 @@ trait MacTileLinkRXClk{ this: MacTileLinkBase =>
// Assembling data that will be written to the rx_fifo // Assembling data that will be written to the rx_fifo
when(reset.asBool){ when(SetWriteRxDataToFifo & ~ShiftWillEnd){
RxDataLatched2 := 0.U
} .elsewhen(SetWriteRxDataToFifo & ~ShiftWillEnd){
RxDataLatched2 := Cat(RxDataLatched1, io.RxData)// Big Endian Byte Ordering RxDataLatched2 := Cat(RxDataLatched1, io.RxData)// Big Endian Byte Ordering
} .elsewhen(SetWriteRxDataToFifo & ShiftWillEnd){ } .elsewhen(SetWriteRxDataToFifo & ShiftWillEnd){
RxDataLatched2 := Mux1H(Seq( RxDataLatched2 := Mux1H(Seq(
@@ -1562,18 +1492,14 @@ trait MacTileLinkRXClk{ this: MacTileLinkBase =>
)) ))
} }
when(reset.asBool){ when(SetWriteRxDataToFifo & ~io.RxAbort){
WriteRxDataToFifo := false.B
} .elsewhen(SetWriteRxDataToFifo & ~io.RxAbort){
WriteRxDataToFifo := true.B WriteRxDataToFifo := true.B
} .elsewhen(WriteRxDataToFifoSync2 | io.RxAbort){ } .elsewhen(WriteRxDataToFifoSync2 | io.RxAbort){
WriteRxDataToFifo := false.B WriteRxDataToFifo := false.B
} }
when(reset.asBool){ when(io.RxStartFrm & ~SyncRxStartFrm_q){
LatchedRxStartFrm := false.B
} .elsewhen(io.RxStartFrm & ~SyncRxStartFrm_q){
LatchedRxStartFrm := true.B LatchedRxStartFrm := true.B
} .elsewhen(SyncRxStartFrm_q){ } .elsewhen(SyncRxStartFrm_q){
LatchedRxStartFrm := false.B LatchedRxStartFrm := false.B
@@ -1581,82 +1507,39 @@ trait MacTileLinkRXClk{ this: MacTileLinkBase =>
// Generation of the end-of-frame signal // Generation of the end-of-frame signal
when(reset.asBool){ when(~io.RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd){
ShiftEnded_rck := false.B
} .elsewhen(~io.RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd){
ShiftEnded_rck := true.B ShiftEnded_rck := true.B
} .elsewhen(io.RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2){ } .elsewhen(io.RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2){
ShiftEnded_rck := false.B ShiftEnded_rck := false.B
} }
when(reset.asBool){
ShiftEndedSync_c1 := false.B
ShiftEndedSync_c2 := false.B
} .otherwise{
ShiftEndedSync_c1 := ShiftEndedSync2
ShiftEndedSync_c2 := ShiftEndedSync_c1
}
// Generation of the end-of-frame signal // Generation of the end-of-frame signal
when(reset.asBool){ when(io.RxStartFrm){
RxEnableWindow := false.B
} .elsewhen(io.RxStartFrm){
RxEnableWindow := true.B RxEnableWindow := true.B
} .elsewhen(io.RxEndFrm | io.RxAbort){ } .elsewhen(io.RxEndFrm | io.RxAbort){
RxEnableWindow := false.B RxEnableWindow := false.B
} }
when(reset.asBool){ when(RxAbortSyncb2){
RxAbortSyncb1 := false.B
RxAbortSyncb2 := false.B
} .otherwise{
RxAbortSyncb1 := RxAbortSync2
RxAbortSyncb2 := RxAbortSyncb1
}
when(reset.asBool){
RxAbortLatched := false.B
} .elsewhen(RxAbortSyncb2){
RxAbortLatched := false.B RxAbortLatched := false.B
} .elsewhen(io.RxAbort){ } .elsewhen(io.RxAbort){
RxAbortLatched := true.B RxAbortLatched := true.B
} }
when(io.LoadRxStatus){
when(reset.asBool){
LatchedRxLength := 0.U
} .elsewhen(io.LoadRxStatus){
LatchedRxLength := io.RxLength LatchedRxLength := io.RxLength
} }
when(reset.asBool){ when(io.LoadRxStatus){
RxStatusInLatched := 0.U
} .elsewhen(io.LoadRxStatus){
RxStatusInLatched := RxStatusIn RxStatusInLatched := RxStatusIn
} }
when(reset.asBool){ val Busy_IRQ_rck = RegInit(false.B); Busy_IRQ_rck_rxclk := Busy_IRQ_rck
RxStatusWriteLatched_sync1 := false.B
RxStatusWriteLatched_sync2 := false.B
} .otherwise{
RxStatusWriteLatched_sync1 := RxStatusWriteLatched;
RxStatusWriteLatched_sync2 := RxStatusWriteLatched_sync1;
}
when(io.RxValid & io.RxStartFrm & ~RxReady){
val Busy_IRQ_rck = Reg(Bool()); Busy_IRQ_rck_rxclk := Busy_IRQ_rck
when(reset.asBool){
Busy_IRQ_rck := false.B
} .elsewhen(io.RxValid & io.RxStartFrm & ~RxReady){
Busy_IRQ_rck := true.B Busy_IRQ_rck := true.B
} .elsewhen(Busy_IRQ_syncb2){ } .elsewhen(Busy_IRQ_syncb2){
Busy_IRQ_rck := false.B Busy_IRQ_rck := false.B