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加入中断寄存器，加入两个32bits寄存器

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This commit is contained in:
Ruige Lee
2025-02-20 19:04:30 +08:00
parent b010d8704e
commit 598982cc95
1 changed files with 74 additions and 45 deletions
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115
src/main/scala/backBoard/ebus/RoCC2CDR.scala
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@@ -317,7 +317,27 @@ trait RoCC2CDRImplLimitTimmer{ this: RoCC2CDRImplBase =>
}
trait RoCC2CDRImplOutTimmer{ this: RoCC2CDRImplBase =>
val isTxBusy: Seq[Bool]
val timeOutCnt = for( _ <- 0 until 2 ) yield { RegInit(0.U(32.W)) }
val isTLClearTimeOut = for( _ <- 0 until 2 ) yield { Wire(Bool()) }
val isTLReadTimeOut = for( _ <- 0 until 2 ) yield { Wire(Bool()) }
val isTxClearTimeOut = for( i <- 0 until 2 ) yield { ~RegNext(isTxBusy(i)) & isTxBusy(i) }
for( i <- 0 until 2 ) {
when( isTLClearTimeOut(i) | isTxClearTimeOut(i) ){
timeOutCnt(i) := 0.U
} .otherwise{
timeOutCnt(i) := timeOutCnt(i) + 1.U
}
}
}
@@ -328,7 +348,7 @@ class RoCC2CDRImpl(outer: RoCC2CDR)(implicit p: Parameters) extends RoCC2CDRImpl
with RoCC2CDRImplTx with RoCC2CDRImplRx
with RoCC2CDRImplIsLast
with RoCC2CDRImplUserCRC
with RoCC2CDRImplLimitTimmer
with RoCC2CDRImplLimitTimmer with RoCC2CDRImplOutTimmer
{
@@ -340,15 +360,6 @@ with RoCC2CDRImplLimitTimmer
io.mem.s2_kill := false.B
io.mem.keep_clock_enabled := false.B
// io.interrupt = Output(Bool())
// io.exception = Input(Bool())
io.fpu_req.valid := false.B
io.fpu_req.bits := DontCare
io.fpu_resp.ready := true.B
@@ -372,46 +383,50 @@ with RoCC2CDRImplLimitTimmer
isTLWriteTxLen(0) := io.cmd.fire & io.cmd.bits.inst.funct === 1.U
isTLWriteTxFifo(0) := io.cmd.fire & io.cmd.bits.inst.funct === 2.U
isTLReadTxCrc(0) := io.cmd.fire & io.cmd.bits.inst.funct === 3.U
isTLClearTimeOut(0) := io.cmd.fire & io.cmd.bits.inst.funct === 4.U & io.cmd.bits.inst.xs1
isTLReadTimeOut(0) := io.cmd.fire & io.cmd.bits.inst.funct === 4.U & io.cmd.bits.inst.xd
isTLWriteSoftReset(1) := io.cmd.fire & io.cmd.bits.inst.funct === 4.U
isTLWriteTxLen(1) := io.cmd.fire & io.cmd.bits.inst.funct === 5.U
isTLWriteTxFifo(1) := io.cmd.fire & io.cmd.bits.inst.funct === 6.U
isTLReadTxCrc(1) := io.cmd.fire & io.cmd.bits.inst.funct === 7.U
isTLWriteSoftReset(1) := io.cmd.fire & io.cmd.bits.inst.funct === 5.U
isTLWriteTxLen(1) := io.cmd.fire & io.cmd.bits.inst.funct === 6.U
isTLWriteTxFifo(1) := io.cmd.fire & io.cmd.bits.inst.funct === 7.U
isTLReadTxCrc(1) := io.cmd.fire & io.cmd.bits.inst.funct === 8.U
isTLClearTimeOut(1) := io.cmd.fire & io.cmd.bits.inst.funct === 9.U & io.cmd.bits.inst.xs1
isTLReadTimeOut(1) := io.cmd.fire & io.cmd.bits.inst.funct === 9.U & io.cmd.bits.inst.xd
isTLWriteSoftReset(2) := io.cmd.fire & io.cmd.bits.inst.funct === 8.U
isTLReadRxLen(0) := io.cmd.fire & io.cmd.bits.inst.funct === 9.U
isTLReadRxFifo(0) := io.cmd.fire & io.cmd.bits.inst.funct === 10.U
isTLReadRxCrc(0) := io.cmd.fire & io.cmd.bits.inst.funct === 11.U
isTLWriteLimitTimerAim(0) := io.cmd.fire & io.cmd.bits.inst.funct === 12.U
isTLWriteLimitTxPair(0) := io.cmd.fire & io.cmd.bits.inst.funct === 13.U
isTLWriteSoftReset(2) := io.cmd.fire & io.cmd.bits.inst.funct === 10.U
isTLReadRxLen(0) := io.cmd.fire & io.cmd.bits.inst.funct === 11.U
isTLReadRxFifo(0) := io.cmd.fire & io.cmd.bits.inst.funct === 12.U
isTLReadRxCrc(0) := io.cmd.fire & io.cmd.bits.inst.funct === 13.U
isTLWriteLimitTimerAim(0) := io.cmd.fire & io.cmd.bits.inst.funct === 14.U
isTLWriteLimitTxPair(0) := io.cmd.fire & io.cmd.bits.inst.funct === 15.U
isTLWriteSoftReset(3) := io.cmd.fire & io.cmd.bits.inst.funct === 14.U
isTLReadRxLen(1) := io.cmd.fire & io.cmd.bits.inst.funct === 15.U
isTLReadRxFifo(1) := io.cmd.fire & io.cmd.bits.inst.funct === 16.U
isTLReadRxCrc(1) := io.cmd.fire & io.cmd.bits.inst.funct === 17.U
isTLWriteLimitTimerAim(1) := io.cmd.fire & io.cmd.bits.inst.funct === 18.U
isTLWriteLimitTxPair(1) := io.cmd.fire & io.cmd.bits.inst.funct === 19.U
isTLWriteSoftReset(3) := io.cmd.fire & io.cmd.bits.inst.funct === 16.U
isTLReadRxLen(1) := io.cmd.fire & io.cmd.bits.inst.funct === 17.U
isTLReadRxFifo(1) := io.cmd.fire & io.cmd.bits.inst.funct === 18.U
isTLReadRxCrc(1) := io.cmd.fire & io.cmd.bits.inst.funct === 19.U
isTLWriteLimitTimerAim(1) := io.cmd.fire & io.cmd.bits.inst.funct === 20.U
isTLWriteLimitTxPair(1) := io.cmd.fire & io.cmd.bits.inst.funct === 21.U
isTLReadStatus := io.cmd.fire & io.cmd.bits.inst.funct === 20.U
isReadIsLast := io.cmd.fire & io.cmd.bits.inst.funct === 21.U
isTLReadStatus := io.cmd.fire & io.cmd.bits.inst.funct === 22.U
val isTLReadInterrupt = io.cmd.fire & io.cmd.bits.inst.funct === 23.U & io.cmd.bits.inst.xd
val isTLClearInterrupt = io.cmd.fire & io.cmd.bits.inst.funct === 23.U & io.cmd.bits.inst.xs1
isReadIsLast := io.cmd.fire & io.cmd.bits.inst.funct === 24.U
// int(0) := intTxEnd(0)
// int(1) := intTxEnd(1)
val interruptReg = RegInit(0.U(32.W))
// int(2) := intRxError(0)
// int(3) := intRxError(1)
when( isTLClearInterrupt ){
interruptReg := interruptReg & ~wdata
} .otherwise{
interruptReg := interruptReg | Cat(
intTxEnd(1), intTxEnd(0),
intRxError(1), intRxError(0),
intRxStart(1), intRxStart(0),
intRxEnd(1), intRxEnd(0),
intTxFifoDeq(1), intTxFifoDeq(0),
intRxFifoEnq(1), intRxFifoEnq(0)
)
}
// int(4) := intRxStart(0)
// int(5) := intRxStart(1)
// int(6) := intRxEnd(0)
// int(7) := intRxEnd(1)
// int(8) := intTxFifoDeq(0)
// int(9) := intTxFifoDeq(1)
// int(10) := intRxFifoEnq(0)
// int(11) := intRxFifoEnq(1)
io.interrupt :=
intTxEnd(0) |
@@ -481,8 +496,15 @@ with RoCC2CDRImplLimitTimmer
rdata := rxCrc(0).io.crc
} .elsewhen(isTLReadRxCrc(1)){
rdata := rxCrc(1).io.crc
} .elsewhen(isTLReadInterrupt){
rdata := interruptReg
} .elsewhen(isTLReadTimeOut(0)){
rdata := timeOutCnt(0)
} .elsewhen(isTLReadTimeOut(1)){
rdata := timeOutCnt(1)
}
when( io.resp.fire ){ //允许连续触发
respValid := false.B
} .elsewhen( isTLReadStatus ){
@@ -505,7 +527,14 @@ with RoCC2CDRImplLimitTimmer
respValid := true.B
} .elsewhen(isTLReadRxCrc(1)){
respValid := true.B
} .elsewhen(isTLReadInterrupt){
respValid := true.B
} .elsewhen(isTLReadTimeOut(0)){
respValid := true.B
} .elsewhen(isTLReadTimeOut(1)){
respValid := true.B
}
}