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同步脉冲模式测试通过

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This commit is contained in:
Ruige Lee
2025-05-16 16:05:38 +08:00
parent 3f1fdc725a
commit 58fbbdd1fc
3 changed files with 114 additions and 12 deletions
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19
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -138,9 +138,9 @@ class SlaveRegisterBundle extends Bundle{
class InterfaceIO extends Bundle{
val ospi = new SSPIInterfaceIO
val oqspi = new QSPIInterfaceIO
val iqspi = Flipped(new QSPIInterfaceIO)
val iqspi = new QSPIInterfaceIO
val lvds = new RegAccessInterfaceIO
val lvds = Flipped(new RegAccessInterfaceIO)
@@ -188,7 +188,7 @@ abstract class InterfaceBase extends Module{
val cReg = Wire(new CommonRegisterBundle); io.cReg := cReg
val mReg = Wire(new MasterRegisterBundle); io.mReg := mReg
val sReg = Wire(new SlaveRegisterBundle)
val sReg = Wire(new SlaveRegisterBundle); io.sReg := sReg
val syncCfg = RegInit(0.U(8.W)); sReg.syncCfg := syncCfg
@@ -562,7 +562,7 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
// io.lvds.isEnW = Output(Bool())
// io.lvds.isEnR = Output(Bool())
io.lvds.datar = RegEnable( AcquireReg(addr = io.lvds.addrSel), 0.U, io.lvds.isEnR )
io.lvds.datar := RegEnable( AcquireReg(addr = io.lvds.addrSel), 0.U, io.lvds.isEnR )
when( io.lvds.isEnW & isSlvMode ){
@@ -643,7 +643,7 @@ trait InterfaceSync{ this: InterfaceBase =>
when( cReg.syncPoint === sReg.recoTimeStamp ){ //时间到达sync0时间点
syncSign(0) := true.B
cReg.syncPoint := cReg.syncPoint + cReg.syncPeroid
syncPoint := syncPoint + cReg.syncPeroid
} .elsewhen( ~sReg.syncCfg(4+0) & syncResetCnt(0) === sReg.syncWidth(0) ){
syncSign(0) := false.B
} .elsewhen( sReg.syncCfg(4+0) & isEnW & addrSel === "h122".U ){
@@ -654,7 +654,7 @@ trait InterfaceSync{ this: InterfaceBase =>
when( cReg.syncPoint === sReg.recoTimeStamp ){ //时间到达sync0时间点
syncOffsetCnt(i) := 0.U
} .elsewhen( syncOffsetCnt(i) < sReg.syncOffset(i) ){
} .elsewhen( syncOffsetCnt(i) <= sReg.syncOffset(i) ){
syncOffsetCnt(i) := syncOffsetCnt(i) + 1.U
}
@@ -669,11 +669,16 @@ trait InterfaceSync{ this: InterfaceBase =>
}
for( i <- 0 until 4 ){
when( ~sReg.syncCfg(4+i) & syncSign(i) ){
when( ~sReg.syncCfg(4+i) ){
when( syncSign(i) ){
syncResetCnt(i) := syncResetCnt(i) + 1.U
} .otherwise{
syncResetCnt(i) := 0.U
}
}
}

6
src/main/scala/backBoard/shin/SlaveParser.scala
View File

@@ -47,7 +47,7 @@ class SlaveParserIO extends Bundle{
val trigAddr = Input( Vec(8, UInt(15.W)) )
val mstDeltaTimeStamp = Output(UInt(32.W))
val slvDeltaTimeStamp = Output(UInt(32.W))
val slvDeltaTime = Output(UInt(32.W))
val deltaFinal = Output(UInt(32.W))
val isLoop = Output(Bool())
@@ -472,6 +472,8 @@ trait SlaveParserRW{ this: SlaveParserBase =>
( upRecParser.io.stateCurr === STATE_PAYLOAD_DATA ) -> addrr,
))
val isRDReg = (readSMAddr(14,11) === "b0000".U)
val isRDSM1 = (readSMAddr(14,11) === "b0010".U)
val isRDSM3 = (readSMAddr(14,11) === "b0100".U)
@@ -552,7 +554,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
val upTimeStamp = Reg(UInt(64.W)) //上行本地时间戳寄存器
val mstTimeStamp = Reg(UInt(64.W)) //主站时间戳
val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
val slvDeltaTimeStamp = Reg(UInt(32.W)); io.slvDeltaTime := slvDeltaTime //从站时间戳差值
val slvDeltaTimeStamp = Reg(UInt(32.W)); io.slvDeltaTime := slvDeltaTimeStamp //从站时间戳差值
val mstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主发从接时间差(中间变量)
val deltaMstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主差从差时间差(中间变量)

99
tb/shinTest/ShinTopSpiTb.v
View File

@@ -517,7 +517,7 @@ initial begin
//子报文
txBuf[132+3] = 8'h0;
txBuf[133+3] = 8'hc; //index = 3
txBuf[134+3] = 8'h09; //地址 //SM1
txBuf[134+3] = 8'h10; //地址 //SM1
txBuf[135+3] = 8'h40; //地址 //偏置
txBuf[136+3] = 8'h00; //命令0 长度56
txBuf[137+3] = 8'd56; //长度
@@ -624,7 +624,7 @@ initial begin
//写入替换时间戳替换地址
txBuf[0+3] = 8'h0c;
txBuf[1+3] = 8'hc0;
spi_trans( (16'h25), (`SPI_WRITE), (2), (0) ); //写入SM1
spi_trans( (16'h25), (`SPI_WRITE), (2), (0) ); //写入替换时间戳替换地址寄存器
//发布请求
txBuf[0+3] = 8'h18;
@@ -635,6 +635,101 @@ initial begin
spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送
@(posedge isResp) #5 begin end
//清除替换时间戳替换地址
txBuf[0+3] = 8'h00;
txBuf[1+3] = 8'h00;
spi_trans( (16'h25), (`SPI_WRITE), (2), (0) ); //清除替换时间戳替换地址寄存器
//设定sync信号
//设置SM1在写入51地址触发enq
txBuf[0+3] = 8'd51;
txBuf[1+3] = 8'h00;
spi_trans( (16'h0202), (`SPI_WRITE), (2), (0) );
//header
txBuf[0+3] = 8'h03;
txBuf[1+3] = 8'h00;//heeader length 48
txBuf[2+3] = 8'h00;
txBuf[3+3] = 8'h00;
//子报文
//设置同步相关寄存器
txBuf[4+3] = 8'h0; //设备索引
txBuf[5+3] = 8'h08; //设备索引、类型 //2号设备
txBuf[6+3] = 8'h01; //地址
txBuf[7+3] = 8'h20; //地址 0x120
txBuf[8+3] = 8'h10; //命令1 写入寄存器 负载长度2
txBuf[9+3] = 8'h28; //负载长度0x28
txBuf[10+3] = 8'h0; //工作计数0
txBuf[11+3] = 8'h0; //工作计数0
txBuf[12+3] = 8'h0f; //负载0x120 0x0f 全部脉冲，全部使能
txBuf[13+3] = 0; //负载0x121
txBuf[14+3] = 10; //负载0x122 sync0脉冲宽度 10
txBuf[15+3] = 0; //负载0x123
txBuf[16+3] = 0; //负载0x124 sync1脉冲宽度 0
txBuf[17+3] = 0; //负载0x125
txBuf[18+3] = 1; //负载0x126 sync2脉冲宽度 1
txBuf[19+3] = 0; //负载0x127
txBuf[20+3] = 8'hff; //负载0x128 sync3脉冲宽度 最大
txBuf[21+3] = 8'hff; //负载0x129
txBuf[22+3] = 0; //负载0x12a empty
txBuf[23+3] = 0; //负载0x12b
txBuf[24+3] = 0; //负载0x12c
txBuf[25+3] = 0; //负载0x12d
txBuf[26+3] = 0; //负载0x12e
txBuf[27+3] = 0; //负载0x12f
//同步点
txBuf[28+3] = 8'h90; //负载0x130 同步点
txBuf[29+3] = 8'h88; //负载0x131
txBuf[30+3] = 0; //负载0x132
txBuf[31+3] = 0; //负载0x133
txBuf[32+3] = 0; //负载0x134
txBuf[33+3] = 0; //负载0x135
txBuf[34+3] = 0; //负载0x136
txBuf[35+3] = 0; //负载0x137
//周期
txBuf[36+3] = 8'hff; //负载0x138
txBuf[37+3] = 0; //负载0x139
txBuf[38+3] = 0; //负载0x13a
txBuf[39+3] = 0; //负载0x13b
//0ffset sync1
txBuf[40+3] = 8'ha; //负载0x13c
txBuf[41+3] = 0; //负载0x13d
txBuf[42+3] = 0; //负载0x13e
txBuf[43+3] = 0; //负载0x13f
//0ffset sync2
txBuf[44+3] = 8'h0; //负载0x140
txBuf[45+3] = 0; //负载0x141
txBuf[46+3] = 0; //负载0x142
txBuf[47+3] = 0; //负载0x143
//0ffset sync3
txBuf[48+3] = 8'h0; //负载0x144
txBuf[49+3] = 8'h01; //负载0x145
txBuf[50+3] = 0; //负载0x146
txBuf[51+3] = 0; //负载0x147
spi_trans( (16'h1000), (`SPI_WRITE), (52), (0) ); //写入SM1
//发布请求
txBuf[0+3] = 8'd52;
txBuf[1+3] = 8'h00;
spi_trans( (16'h21), (`SPI_WRITE), (2), (0) );//写入长度
txBuf[0+3] = 8'h01;
spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送
@(posedge isResp) #5 begin end
end