同步脉冲模式测试通过
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@@ -47,7 +47,7 @@ class SlaveParserIO extends Bundle{
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val trigAddr = Input( Vec(8, UInt(15.W)) )
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val mstDeltaTimeStamp = Output(UInt(32.W))
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val slvDeltaTimeStamp = Output(UInt(32.W))
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val slvDeltaTime = Output(UInt(32.W))
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val deltaFinal = Output(UInt(32.W))
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val isLoop = Output(Bool())
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@@ -472,6 +472,8 @@ trait SlaveParserRW{ this: SlaveParserBase =>
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( upRecParser.io.stateCurr === STATE_PAYLOAD_DATA ) -> addrr,
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))
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val isRDReg = (readSMAddr(14,11) === "b0000".U)
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val isRDSM1 = (readSMAddr(14,11) === "b0010".U)
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val isRDSM3 = (readSMAddr(14,11) === "b0100".U)
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@@ -552,7 +554,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
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val upTimeStamp = Reg(UInt(64.W)) //上行本地时间戳寄存器
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val mstTimeStamp = Reg(UInt(64.W)) //主站时间戳
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val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
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val slvDeltaTimeStamp = Reg(UInt(32.W)); io.slvDeltaTime := slvDeltaTime //从站时间戳差值
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val slvDeltaTimeStamp = Reg(UInt(32.W)); io.slvDeltaTime := slvDeltaTimeStamp //从站时间戳差值
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val mstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主发从接时间差(中间变量)
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val deltaMstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主差从差时间差(中间变量)
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