同步脉冲模式测试通过

src/main/scala/backBoard/shin/Interface.scala

@@ -138,9 +138,9 @@ class SlaveRegisterBundle extends Bundle{
 class InterfaceIO extends Bundle{
   val ospi = new SSPIInterfaceIO
   val oqspi = new QSPIInterfaceIO
-  val iqspi = Flipped(new QSPIInterfaceIO)
+  val iqspi = new QSPIInterfaceIO
 
-  val lvds  = new RegAccessInterfaceIO
+  val lvds  = Flipped(new RegAccessInterfaceIO)
 
 
 
@@ -188,7 +188,7 @@ abstract class InterfaceBase extends Module{
 
   val cReg = Wire(new CommonRegisterBundle); io.cReg := cReg
   val mReg = Wire(new MasterRegisterBundle); io.mReg := mReg
-  val sReg = Wire(new SlaveRegisterBundle)
+  val sReg = Wire(new SlaveRegisterBundle);  io.sReg := sReg
 
   val syncCfg = RegInit(0.U(8.W)); sReg.syncCfg := syncCfg
 
@@ -562,7 +562,7 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
   // io.lvds.isEnW   = Output(Bool())
   // io.lvds.isEnR   = Output(Bool())
 
-  io.lvds.datar = RegEnable( AcquireReg(addr = io.lvds.addrSel), 0.U, io.lvds.isEnR )
+  io.lvds.datar := RegEnable( AcquireReg(addr = io.lvds.addrSel), 0.U, io.lvds.isEnR )
 
   when( io.lvds.isEnW & isSlvMode ){
 
@@ -643,7 +643,7 @@ trait InterfaceSync{ this: InterfaceBase =>
 
   when( cReg.syncPoint === sReg.recoTimeStamp ){ //时间到达sync0时间点
     syncSign(0) := true.B
-    cReg.syncPoint := cReg.syncPoint + cReg.syncPeroid
+    syncPoint := syncPoint + cReg.syncPeroid
   } .elsewhen( ~sReg.syncCfg(4+0) & syncResetCnt(0) === sReg.syncWidth(0) ){
     syncSign(0) := false.B
   } .elsewhen( sReg.syncCfg(4+0) & isEnW & addrSel === "h122".U ){
@@ -654,7 +654,7 @@ trait InterfaceSync{ this: InterfaceBase =>
 
     when( cReg.syncPoint === sReg.recoTimeStamp ){ //时间到达sync0时间点
       syncOffsetCnt(i) := 0.U
-    } .elsewhen( syncOffsetCnt(i) < sReg.syncOffset(i) ){
+    } .elsewhen( syncOffsetCnt(i) <= sReg.syncOffset(i) ){
       syncOffsetCnt(i) := syncOffsetCnt(i) + 1.U
     }
 
@@ -669,9 +669,14 @@ trait InterfaceSync{ this: InterfaceBase =>
   }
 
   for( i <- 0 until 4 ){
-    when( ~sReg.syncCfg(4+i) & syncSign(i) ){
-      syncResetCnt(i) := syncResetCnt(i) + 1.U
+    when( ~sReg.syncCfg(4+i) ){
+      when( syncSign(i) ){
+        syncResetCnt(i) := syncResetCnt(i) + 1.U
+      } .otherwise{
+        syncResetCnt(i) := 0.U
+      }
     }
+
   }
 
 

src/main/scala/backBoard/shin/SlaveParser.scala

@@ -47,7 +47,7 @@ class SlaveParserIO extends Bundle{
   val trigAddr = Input( Vec(8, UInt(15.W)) )
 
   val mstDeltaTimeStamp = Output(UInt(32.W))
-  val slvDeltaTimeStamp = Output(UInt(32.W))
+  val slvDeltaTime = Output(UInt(32.W))
   val deltaFinal        = Output(UInt(32.W))
 
   val isLoop = Output(Bool())
@@ -472,6 +472,8 @@ trait SlaveParserRW{ this: SlaveParserBase =>
     ( upRecParser.io.stateCurr === STATE_PAYLOAD_DATA    ) -> addrr,
   ))
 
+
+
   val isRDReg      = (readSMAddr(14,11) === "b0000".U)
   val isRDSM1      = (readSMAddr(14,11) === "b0010".U)
   val isRDSM3      = (readSMAddr(14,11) === "b0100".U)
@@ -552,7 +554,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
   val upTimeStamp   = Reg(UInt(64.W)) //上行本地时间戳寄存器
   val mstTimeStamp  = Reg(UInt(64.W)) //主站时间戳
   val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
-  val slvDeltaTimeStamp = Reg(UInt(32.W)); io.slvDeltaTime := slvDeltaTime //从站时间戳差值
+  val slvDeltaTimeStamp = Reg(UInt(32.W)); io.slvDeltaTime := slvDeltaTimeStamp //从站时间戳差值
 
   val mstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主发从接时间差(中间变量)
   val deltaMstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主差从差时间差(中间变量)