处理顺序索引和同步

2025-04-21 18:48:29 +08:00
parent 3277e76e19
commit 58eb3c0aed
1 changed files with 159 additions and 31 deletions
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -42,6 +42,8 @@ class SlaveParserIO extends Bundle{

  val dSMenq = Vec(4, Decoupled(UInt(8.W)))
  val uSMdeq = Vec(4, Flipped(Decoupled(UInt(8.W))))
+
+  val timeStamp = Input(UInt(64.W))
 }

 abstract class SlaveParserBase extends Module{
@@ -72,10 +74,11 @@ abstract class SlaveParserBase extends Module{
  val upSendGen   = Module(new SlaveSendGen)


-  val localDevIndex = Reg(UInt(14.W)) //当前设备索引
+  val localDevIndex = RegInit(0.U(14.W)) //当前设备索引
  dontTouch(localDevIndex)


+
  // 认为只有下行到下行，上行到上行模式，探针是独立发起操作
  // val downSinkSel = Reg(Bool())
  // val upSinkSel = Reg(Bool())
@@ -187,29 +190,44 @@ abstract class SlaveParserBase extends Module{
      downSubMsgInfo(0).address  := downRecParser.io.subMsgReq.bits.address
      downSubMsgInfo(0).operator := downRecParser.io.subMsgReq.bits.operator
      downSubMsgInfo(0).length   := downRecParser.io.subMsgReq.bits.length
-      downSubMsgInfo(0).workCnt  := 
-        Mux(
-          downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & (//自身包
-            (downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 3.U) //写操作或读写操作
-          ), downRecParser.io.subMsgReq.bits.workCnt + 1.U, downRecParser.io.subMsgReq.bits.workCnt
-        )
-        
+      downSubMsgInfo(0).workCnt  := downRecParser.io.subMsgReq.bits.workCnt
      downSubMsgInfo(0).source := 0.U

-    } .otherwise{
+      //override
+      when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 3.U) ) ) { //自身包//写操作或读写操作)
+        downSubMsgInfo(0).workCnt  := downRecParser.io.subMsgReq.bits.workCnt + 1.U
+      }
+
+      when(
+        downRecParser.io.subMsgReq.bits.devIndex === 0.U &
+        downRecParser.io.subMsgReq.bits.style === 0.U &
+        downRecParser.io.subMsgReq.bits.operator === "hd".U ){ //设置顺序地址
+          localDevIndex := downRecParser.io.subMsgReq.bits.workCnt + 1.U
+          downSubMsgInfo(0).workCnt  := downRecParser.io.subMsgReq.bits.workCnt + 1.U
+      }
+
+    } .otherwise{ //pong
      downSubMsgInfo(1).devIndex := downRecParser.io.subMsgReq.bits.devIndex
      downSubMsgInfo(1).style    := downRecParser.io.subMsgReq.bits.style
      downSubMsgInfo(1).address  := downRecParser.io.subMsgReq.bits.address
      downSubMsgInfo(1).operator := downRecParser.io.subMsgReq.bits.operator
      downSubMsgInfo(1).length   := downRecParser.io.subMsgReq.bits.length
-      downSubMsgInfo(1).workCnt  := 
-        Mux(
-          downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & (//自身包
-            (downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 3.U) //写操作或读写操作
-          ), downRecParser.io.subMsgReq.bits.workCnt + 1.U, downRecParser.io.subMsgReq.bits.workCnt
-        )
+      downSubMsgInfo(1).workCnt  := downRecParser.io.subMsgReq.bits.workCnt
      downSubMsgInfo(1).source := 1.U

+      //override
+      when( downRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (downRecParser.io.subMsgReq.bits.operator === 1.U) | (downRecParser.io.subMsgReq.bits.operator === 3.U) )) { //自身包//写操作或读写操作 )
+        downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
+      }
+
+      when(
+        downRecParser.io.subMsgReq.bits.devIndex === 0.U &
+        downRecParser.io.subMsgReq.bits.style === 0.U &
+        downRecParser.io.subMsgReq.bits.operator === "hd".U ){ //设置顺序地址
+          localDevIndex := downRecParser.io.subMsgReq.bits.workCnt + 1.U
+          downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
+      }
+
    }
  }

@@ -284,33 +302,38 @@ abstract class SlaveParserBase extends Module{
      upSubMsgInfo(0).address  := upRecParser.io.subMsgReq.bits.address
      upSubMsgInfo(0).operator := upRecParser.io.subMsgReq.bits.operator
      upSubMsgInfo(0).length   := upRecParser.io.subMsgReq.bits.length
-      upSubMsgInfo(0).workCnt  :=
-        Mux(
-          upRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( //自身包
-            (upRecParser.io.subMsgReq.bits.operator === 2.U) || (upRecParser.io.subMsgReq.bits.operator === 3.U) //读或读写
-          ), upRecParser.io.subMsgReq.bits.workCnt + 1.U, upRecParser.io.subMsgReq.bits.workCnt
-        )
+      upSubMsgInfo(0).workCnt  := upRecParser.io.subMsgReq.bits.workCnt
      upSubMsgInfo(0).source := 0.U
+
+      //override
+      when( upRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (upRecParser.io.subMsgReq.bits.operator === 2.U) || (upRecParser.io.subMsgReq.bits.operator === 3.U) ) ){ //自身包//读或读写
+        upSubMsgInfo(0).workCnt  := upRecParser.io.subMsgReq.bits.workCnt + 1.U
+      }
+
    } .otherwise{
      upSubMsgInfo(1).devIndex := upRecParser.io.subMsgReq.bits.devIndex
      upSubMsgInfo(1).style    := upRecParser.io.subMsgReq.bits.style
      upSubMsgInfo(1).address  := upRecParser.io.subMsgReq.bits.address
      upSubMsgInfo(1).operator := upRecParser.io.subMsgReq.bits.operator
      upSubMsgInfo(1).length   := upRecParser.io.subMsgReq.bits.length
-      upSubMsgInfo(1).workCnt  := 
-        Mux(
-          upRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( //自身包
-            (upRecParser.io.subMsgReq.bits.operator === 2.U) || (upRecParser.io.subMsgReq.bits.operator === 3.U) //读或读写
-          ), upRecParser.io.subMsgReq.bits.workCnt + 1.U, upRecParser.io.subMsgReq.bits.workCnt
-        )
+      upSubMsgInfo(1).workCnt  := upRecParser.io.subMsgReq.bits.workCnt
      upSubMsgInfo(1).source := 1.U

+      //override
+      when( upRecParser.io.subMsgReq.bits.devIndex === localDevIndex & ( (upRecParser.io.subMsgReq.bits.operator === 2.U) || (upRecParser.io.subMsgReq.bits.operator === 3.U) )){ //自身包//读或读写 )
+        upSubMsgInfo(1).workCnt  := upRecParser.io.subMsgReq.bits.workCnt + 1.U
+      }
+
    }
  }


  //读出uSM  

+  val isReadSM = 
+    ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (upSubMsgInfo(0).devIndex === localDevIndex) & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U)) |
+    ((upRecParser.io.stateNext === STATE_PAYLOAD_DATA) & (upRecParser.io.subMsgReq.bits.devIndex === localDevIndex) & (upRecParser.io.subMsgReq.bits.operator === 2.U | upRecParser.io.subMsgReq.bits.operator === 3.U))
+
  val addrr = Reg(UInt(15.W))  
  val readSMAddr := Mux1H(Seq(
    ( upRecParser.io.stateCurr === STATE_PAYLOAD_WORKCNT ) -> upRecParser.io.subMsgReq.bits.address,
@@ -352,10 +375,10 @@ abstract class SlaveParserBase extends Module{
  }


-  io.uSMdeq(0).ready := ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 0.U )
-  io.uSMdeq(1).ready := ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 1.U )
-  io.uSMdeq(2).ready := ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 2.U )
-  io.uSMdeq(3).ready := ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 3.U )
+  io.uSMdeq(0).ready := isReadSM & ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 0.U )
+  io.uSMdeq(1).ready := isReadSM & ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 1.U )
+  io.uSMdeq(2).ready := isReadSM & ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 2.U )
+  io.uSMdeq(3).ready := isReadSM & ( upRecParser.io.stateNext === STATE_PAYLOAD_DATA ) & ( readSMAddr === 3.U )



@@ -463,8 +486,113 @@ abstract class SlaveParserBase extends Module{

  }

+trait SlaveParserSync{ this: SlaveParserBase =>
+  val downTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器 
+  val upTimeStamp   = Reg(UInt(64.W)) //下行本地时间戳寄存器
+  val mstTimeStamp  = Reg(UInt(64.W)) //主站时间戳
+  val mstDeltaTimeStamp = Reg(UInt(32.W)) //主站时间戳差值
+  val slvDeltaTimeStamp = Reg(UInt(32.W)) //从站时间戳差值
+
+  val mstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主发从接时间差(中间变量)
+
+
+  val recoTimeStamp = Reg(UInt(64.W)) //时钟补偿寄存器
+
+  recoTimeStamp = io.timeStamp + (mstSlvDeltaTimeStamp) +  (mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1
+
+
+  //更新下行本地时间戳寄存器
+  when( downRecParser.io.frameReq.fire ){
+    downTimeStamp := io.timeStamp
+  }
+
+  //更新上行本地时间戳寄存器
+  when( upRecParser.io.frameReq.fire ){
+    upTimeStamp := io.timeStamp
+    slvDeltaTimeStamp := io.timeStamp - downTimeStamp
+  }
+
+  //下行接收
+  val isSync := (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
+    ( ~isDownRecPing & downSubMsgInfo(0).devIndex === 0.U & downSubMsgInfo(0).operator === "he".U ) |
+    (  isDownRecPing & downSubMsgInfo(1).devIndex === 0.U & downSubMsgInfo(1).operator === "he".U )
+  )
+
+  val syncCnt = Reg(UInt(4.W))
+
+  when( isSync ){
+    syncCnt := syncCnt + 1.U
+  } .otherwise{
+    syncCnt := 0.U
+  }
+
+  when( isSync ){
+    when( syncCnt === 0.U ){
+      mstTimeStamp := Cat( downRecParser.io.data.bits, mstTimeStamp(55,0) )
+    } .elsewhen( syncCnt === 1.U ){
+      mstTimeStamp := Cat( mstTimeStamp(63,56), downRecParser.io.data.bits, mstTimeStamp(47,0) )
+    } .elsewhen( syncCnt === 2.U ){
+      mstTimeStamp := Cat( mstTimeStamp(63,48), downRecParser.io.data.bits, mstTimeStamp(39,0) )
+    } .elsewhen( syncCnt === 3.U ){
+      mstTimeStamp := Cat( mstTimeStamp(63,40), downRecParser.io.data.bits, mstTimeStamp(31,0) )
+    } .elsewhen( syncCnt === 4.U ){
+      mstTimeStamp := Cat( mstTimeStamp(63,32), downRecParser.io.data.bits, mstTimeStamp(23,0) )
+    } .elsewhen( syncCnt === 5.U ){
+      mstTimeStamp := Cat( mstTimeStamp(63,24), downRecParser.io.data.bits, mstTimeStamp(15,0) )
+    } .elsewhen( syncCnt === 6.U ){
+      mstTimeStamp := Cat( mstTimeStamp(63,16), downRecParser.io.data.bits, mstTimeStamp(7,0) )
+    } .elsewhen( syncCnt === 7.U ){
+      mstTimeStamp := Cat( mstTimeStamp(63, 8), downRecParser.io.data.bits )
+    } .elsewhen( syncCnt === 8.U ){
+      mstSlvDeltaTimeStamp := mstTimeStamp - downTimeStamp
+      mstDeltaTimeStamp := Cat( downRecParser.io.data.bits, mstDeltaTimeStamp(23, 0) )
+    } .elsewhen( syncCnt === 9.U ){
+      mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31,24), downRecParser.io.data.bits, mstDeltaTimeStamp(15,0) )
+    } .elsewhen( syncCnt === 10.U ){
+      mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31,16), downRecParser.io.data.bits, mstDeltaTimeStamp(7,0) )
+    } .elsewhen( syncCnt === 11.U ){
+      mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31, 8), downRecParser.io.data.bits )
+    } .otherwise{
+      assert(false.B, "Wrong Sync SubMsg!\n")
+    }
+  }
+
+
+
+
+
+  io.dSMenq(0).valid := isWriteSM & addrw === 0.U
+  io.dSMenq(0).bits  := downRecParser.io.data.bits
+  when( io.dSMenq(0).valid & ~io.dSMenq(0).ready ){
+    printf("An Error occur at dSMenq0!\n")
+  }
+
+  io.dSMenq(1).valid := isWriteSM & addrw === 1.U
+  io.dSMenq(1).bits  := downRecParser.io.data.bits
+  when( io.dSMenq(1).valid & ~io.dSMenq(1).ready ){
+    printf("An Error occur at dSMenq1!\n")
+  }
+
+  io.dSMenq(2).valid := isWriteSM & addrw === 2.U
+  io.dSMenq(2).bits  := downRecParser.io.data.bits
+  when( io.dSMenq(2).valid & ~io.dSMenq(2).ready ){
+    printf("An Error occur at dSMenq2!\n")
+  }
+
+  io.dSMenq(3).valid := isWriteSM & addrw === 3.U
+  io.dSMenq(3).bits  := downRecParser.io.data.bits
+  when( io.dSMenq(3).valid & ~io.dSMenq(3).ready ){
+    printf("An Error occur at dSMenq3!\n")
+  }
+
+
+
+}
+
+

 class SlaveParser extends SlaveParserBase
+with SlaveParserSync