diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
new file mode 100644
index 0000000..ed8116a
--- /dev/null
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -0,0 +1,142 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+//work in 100MHZ
+class CDRInIO extends Bundle{
+  val axis = Decoupled(new AXIS_Bundle)
+  val serDat = Input(Bool())
+  val overCLK = Input(Bool())
+}
+
+
+abstract class CDRInBase extends Module{
+  def sampleRate: Int = 4
+
+  // require( (sampleRate % 2) == 1 )
+
+  val io: CDRInIO = IO(new CDRInIO)
+
+
+}
+
+trait CDRInOverSample{ this: CDRInBase =>
+  val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
+  val arbResult = VecInit(sampleReg).count( (x:Bool) => (x === true.B) ) > (sampleRate / 2).U
+
+  val syncSerDat = ShiftRegister( arbResult, 2 )
+}
+
+
+trait CDRInAxis{ this: CDRInBase =>
+
+  def HeaderByte: Int = 4
+
+  val ETH_PRE = "h55".U
+  val ETH_SFD = "hD5".U
+
+  val STATE_IDLE = 0.U
+  val STATE_HEADER = 1.U
+  val STATE_PAYLOAD = 2.U
+  val STATE_CRC = 3.U
+
+
+
+
+  val stateNext = Wire(UInt(2.W))
+  val stateCurr = RegNext( stateNext, STATE_IDLE )
+
+  val crcUnit = Module(new crc32_8)
+  val crcOut = crcUnit.io.crc
+  val crcCmp = Reg(UInt(32.W))
+
+  val bitCnt = Reg(UInt(3.W))
+  val byteCnt = Reg(UInt(16.W))
+
+  val syncSerDat: Bool
+  val shiftData = RegInit(0.U(8.W)); shiftData := Cat(shiftData(6,0), syncSerDat)
+
+  val header = Reg(UInt((8*HeaderByte).W))
+  val payloadLen = header(31,16)
+  val operation  = header(15,8)
+  val param      = header( 7,0)
+
+
+  stateNext := 
+    Mux1H(Seq(
+      (stateCurr === STATE_IDLE)    -> ( Mux( (byteCnt === 8.U)            & (bitCnt === 7.U) & (shiftData === ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
+      (stateCurr === STATE_HEADER)  -> ( Mux( (byteCnt === (HeaderByte).U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_HEADER ) ),
+      (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen)  ) & (bitCnt === 7.U), STATE_CRC, STATE_PAYLOAD  )), // PAYLOAD
+      (stateCurr === STATE_CRC)     -> ( Mux( (byteCnt === 4.U)            & (bitCnt === 7.U), STATE_IDLE, STATE_CRC )), //CRC
+    ))
+
+
+
+
+
+  when( byteCnt === 0.U & shiftData === ETH_PRE & stateCurr === STATE_IDLE ){ //first align
+    bitCnt := 0.U
+  } .otherwise{ 
+    bitCnt := bitCnt + 1.U
+  }
+
+
+
+  when( byteCnt === 0.U & shiftData === ETH_PRE & stateCurr === STATE_IDLE ){ //first align
+    byteCnt := 1.U
+  } .elsewhen( bitCnt === 7.U ){
+    when( stateCurr === STATE_IDLE ){
+      byteCnt := Mux( byteCnt =/= 8.U & shiftData === ETH_PRE, byteCnt + 1.U, 0.U)//keep align, align failed or SFD pass
+      assert( byteCnt <= 8.U )
+    } .elsewhen( stateCurr === STATE_HEADER ){
+      byteCnt := Mux( byteCnt =/= (HeaderByte).U, byteCnt + 1.U, 0.U )
+      assert( byteCnt <= (HeaderByte).U )
+    } .elsewhen( stateCurr === STATE_PAYLOAD ){
+      byteCnt := Mux( byteCnt =/= payloadLen, byteCnt + 1.U, 0.U )
+      assert( byteCnt <= payloadLen )
+    } .elsewhen( stateCurr === STATE_CRC ){
+      byteCnt := Mux( byteCnt =/= 4.U, byteCnt + 1.U, 0.U )
+      assert( byteCnt <= 4.U )
+    }
+  }
+
+  when( stateCurr === STATE_HEADER & bitCnt === 7.U ){
+    header := Cat( header( 8*HeaderByte-1-8, 0), shiftData )
+  }
+
+
+
+  val axis_valid = RegInit(false.B)
+  val axis_tdata = RegEnable( shiftData, bitCnt === 7.U & ( stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) )
+  val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 4.U & (crcOut =/= ~Cat( crcCmp(23,0), shiftData )),  bitCnt === 7.U )
+  val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 4.U,                                                 bitCnt === 7.U )
+
+  io.axis.valid := axis_valid
+  io.axis.bits.tdata := axis_tdata
+  io.axis.bits.tuser := axis_tuser
+  io.axis.bits.tlast := axis_tlast
+
+
+  when( io.axis.fire ){
+    axis_valid := false.B
+  } .elsewhen( bitCnt === 7.U & ( stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ){
+    axis_valid := true.B
+  }
+
+  when( stateCurr === STATE_CRC & bitCnt === 7.U ){
+    crcCmp := Cat( crcCmp(23,0), shiftData )
+  }
+
+
+  crcUnit.io.isEnable := ((stateCurr === STATE_HEADER ) | (stateCurr === STATE_PAYLOAD )) & ( bitCnt === 7.U )
+  crcUnit.io.dataIn   := shiftData
+  
+  crcUnit.reset := reset.asBool | ( stateCurr === STATE_IDLE ) //idle
+
+}
+
+
+class CDRIn extends CDRInBase with CDRInOverSample with CDRInAxis
+
diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala
index e8b8167..e9b7a10 100644
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -40,7 +40,11 @@ object testModule extends App {
 
    (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq(
       ChiselGeneratorAnnotation(() => { new CDROut })
-    ))   
+    ))
+
+   (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq(
+      ChiselGeneratorAnnotation(() => { new CDRIn })
+    ))
 
   // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
   //     ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })