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修正模拟代码，更精简的策略

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bacon
2026-02-26 23:39:33 +08:00
parent b7fa4295cd
commit 57ab18a492
1 changed files with 103 additions and 214 deletions
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321
tb/shinTest/shinSim/easybusSim.py
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@@ -50,7 +50,7 @@ class ArrayUintRef:
self.arr[self.index + 6] = ((val >> 48) & 0xff)
self.arr[self.index + 7] = ((val >> 56) & 0xff)
print('setter:', self.t)
#print('setter:', self.t)
def __repr__(self):
return f"ArrayUintRef(value={self.value})"
@@ -160,37 +160,44 @@ class device(object):
self.reg = array.array('B', [0, ] * 2048)
# 配置各SM的item数量（sm0~sm7）
self.sm0 = MemroyQueueMgr(4)
self.sm0_item_n = ArrayUintRef(self.reg, 0x301)
self.sm0_len = ArrayUintRef(self.reg, 0x302, 1)
self.sm = dict()
syncMemNum = [4, 4, 4, 4, 2, 2, 2, 2]
for i in range(8):
self.sm[f'mem{i}'] = MemroyQueueMgr(syncMemNum[i])
self.sm[f'mem{i}_ctrl'] = ArrayUintRef(self.reg, 0x300 + i * 4)
self.sm[f'mem{i}_item_num'] = ArrayUintRef(self.reg, 0x301 + i * 4)
self.sm[f'mem{i}_len'] = ArrayUintRef(self.reg, 0x302 + i * 4, 1)
self.sm1 = MemroyQueueMgr(4)
self.sm1_item_n = ArrayUintRef(self.reg, 0x305)
self.sm1_len = ArrayUintRef(self.reg, 0x306, 1)
#print(self.sm)
self.sm2 = MemroyQueueMgr(4)
self.sm2_item_n = ArrayUintRef(self.reg, 0x309)
self.sm2_len = ArrayUintRef(self.reg, 0x30a, 1)
self.ebmmu = dict()
for i in range(16):
self.ebmmu[f'va{i}'] = ArrayUintRef(self.reg, 0x200 + i * 0xa, 2)
self.ebmmu[f'pa{i}'] = ArrayUintRef(self.reg, 0x204 + i * 0xa, 1)
self.ebmmu[f'op{i}'] = ArrayUintRef(self.reg, 0x208 + i * 0xa, 0)
self.ebmmu[f'en{i}'] = ArrayUintRef(self.reg, 0x209 + i * 0xa, 0)
self.sm3 = MemroyQueueMgr(4)
self.sm3_item_n = ArrayUintRef(self.reg, 0x30d)
self.sm3_len = ArrayUintRef(self.reg, 0x30e, 1)
#看门狗
self.watchdog = dict()
self.watchdog["status"] = ArrayUintRef(self.reg, 0x400, 2)
self.watchdog["enable"] = ArrayUintRef(self.reg, 0x404, 2)
for i in range(18):
self.watchdog[f"{i}"] = ArrayUintRef(self.reg, 0x408 + i * 4, 2)
self.sm4 = MemroyQueueMgr(2)
self.sm4_item_n = ArrayUintRef(self.reg, 0x311)
self.sm4_len = ArrayUintRef(self.reg, 0x312, 1)
self.sm5 = MemroyQueueMgr(2)
self.sm5_item_n = ArrayUintRef(self.reg, 0x315)
self.sm5_len = ArrayUintRef(self.reg, 0x316, 1)
self.sm6 = MemroyQueueMgr(2)
self.sm6_item_n = ArrayUintRef(self.reg, 0x319)
self.sm6_len = ArrayUintRef(self.reg, 0x31a, 1)
self.sm7 = MemroyQueueMgr(2)
self.sm7_item_n = ArrayUintRef(self.reg, 0x31d)
self.sm7_len = ArrayUintRef(self.reg, 0x31e, 1)
#事件
self.event = dict()
self.event['ctrl0'] = ArrayUintRef(self.reg, 0x500, 1)
self.event['ctrl1'] = ArrayUintRef(self.reg, 0x502, 1)
self.event['status0'] = ArrayUintRef(self.reg, 0x504, 1)
self.event['status1'] = ArrayUintRef(self.reg, 0x506, 1)
self.event['rise0'] = ArrayUintRef(self.reg, 0x508, 3)
self.event['fall0'] = ArrayUintRef(self.reg, 0x510, 3)
self.event['rise1'] = ArrayUintRef(self.reg, 0x518, 3)
self.event['fall1'] = ArrayUintRef(self.reg, 0x520, 3)
self.event['host_sm_w'] = ArrayUintRef(self.reg, 0x528, 3)
self.event['host_sm_r'] = ArrayUintRef(self.reg, 0x530, 3)
self.event['lvds_sm_w'] = ArrayUintRef(self.reg, 0x538, 3)
self.event['lvds_sm_r'] = ArrayUintRef(self.reg, 0x540, 3)
#主/从设备
self.role = ArrayUintRef(self.reg, 0)
@@ -213,10 +220,16 @@ class device(object):
self.reg[0x73] = 0x80
self.reg[0x77] = 0x80
self.int_en = ArrayUintRef(self.reg, 0x70, 2)
self.int_status = ArrayUintRef(self.reg, 0x74, 2)
self.int_clear = ArrayUintRef(self.reg, 0x78, 2)
self.int_mode = ArrayUintRef(self.reg, 0x7c, 1)
#SYNC同步点
self.sync_point = ArrayUintRef(self.reg, 0x130, 3)
self.sync_point.value = 0xffffffffffffffff
print('sync_point', self.reg[0x130:0x138], hex(self.sync_point.value))
#print('sync_point', self.reg[0x130:0x138], hex(self.sync_point.value))
'''
self.reg[0x130] = 0xff
@@ -273,17 +286,17 @@ class device(object):
l = len(data)
ret = False
for k, v in enumerate(range(addr, addr+l)):
ret = (self.__ctrl_regs_write(v, data[k])
or self.__reset_ctrl_regs_write(v, data[k])
or self.__int_regs_write(v, data[k])
or self.__stat_regs_write(v, data[k])
or self.__link_regs_write(v, data[k])
or self.__sync_regs_write(v, data[k])
or self.__custom_def_regs_write(v, data[k])
or self.__ebmmu_regs_write(v, data[k])
or self.__sm_regs_write(v, data[k])
or self.__watch_dog_regs_write(v, data[k])
or self.__event_regs_write(v, data[k])
ret = (self.__ctrl_regs_hw(v, data[k])
or self.__reset_ctrl_regs_hw(v, data[k])
or self.__int_regs_hw(v, data[k])
or self.__stat_regs_hw(v, data[k])
or self.__link_regs_hw(v, data[k])
or self.__sync_regs_hw(v, data[k])
or self.__custom_def_regs_hw(v, data[k])
or self.__ebmmu_regs_hw(v, data[k])
or self.__sm_regs_hw(v, data[k])
or self.__watch_dog_regs_hw(v, data[k])
or self.__event_regs_hw(v, data[k])
)
# self.__init_temp_regs()
@@ -306,7 +319,7 @@ class device(object):
pass
def __ctrl_regs_write(self, regaddr, val):
def __ctrl_regs_hw(self, regaddr, val):
if regaddr == 0x00:
self.reg[regaddr] = val & 0xff
@@ -343,7 +356,7 @@ class device(object):
return True
def __reset_ctrl_regs_write(self, regaddr, val):
def __reset_ctrl_regs_hw(self, regaddr, val):
#EasyBus复位
if (regaddr >= 0x40) and (regaddr <= 0x43):
if regaddr == 0x40:
@@ -423,7 +436,7 @@ class device(object):
return True
def __int_regs_write(self, regaddr, val):
def __int_regs_hw(self, regaddr, val):
#中断使能
if (regaddr >= 0x70) and (regaddr <= 0x73):
self.reg[regaddr] = val & 0xff
@@ -449,7 +462,7 @@ class device(object):
return True
def __stat_regs_write(self, regaddr, val):
def __stat_regs_hw(self, regaddr, val):
#统计
#下行接收错误计数器（包括包不完全、CDR、CRC、超时）
if (regaddr >= 0x80) and (regaddr <= 0x81):
@@ -520,7 +533,7 @@ class device(object):
return True
def __link_regs_write(self, regaddr, val):
def __link_regs_hw(self, regaddr, val):
#两个寄存器都是只读
#链路状态
if (regaddr >= 0xc0) and (regaddr <= 0xc1):
@@ -536,7 +549,7 @@ class device(object):
return True
def __sync_regs_write(self, regaddr, val):
def __sync_regs_hw(self, regaddr, val):
#同步
#这里注意一个问题，主站是否要考虑lvds侧锁不锁的问题
if (regaddr >= 0x0100) and (regaddr <= 0x107):
@@ -591,7 +604,7 @@ class device(object):
return True
def __custom_def_regs_write(self, regaddr, val):
def __custom_def_regs_hw(self, regaddr, val):
if (regaddr >= 0x180) and (regaddr <= 0x1FF):
self.reg[regaddr] = val & 0xff
else:
@@ -599,193 +612,69 @@ class device(object):
return True
def __ebmmu_regs_write(self, regaddr, val):
def __ebmmu_regs_hw(self, regaddr, val):
ebmmu_base = 0x200
ebmmu_no = 16
flag = False
for i in range(ebmmu_no):
if (regaddr >= (0x200 + i * 0xa)) and (regaddr <= ((0x200 + i * 0xa) + 0x3)):
if (ebmmu_base + i * 0xa) <= regaddr <= ((ebmmu_base + i * 0xa) + 0x3):
if (self.reg[0x18] & 0x1) == 0x1:
self.reg[regaddr] = val & 0xff
flag = True
elif (regaddr >= ((0x200 + i * 0xa) + 0x4)) and (regaddr <= ((0x200 + i * 0xa) + 0x5)):
elif ((ebmmu_base + i * 0xa) + 0x4) <= regaddr <= ((ebmmu_base + i * 0xa) + 0x5):
if (self.reg[0x18] & 0x1) == 0x1:
self.reg[regaddr] = val & 0xff
flag = True
elif (regaddr >= ((0x200 + i * 0xa) + 0x6)) and (regaddr <= ((0x200 + i * 0xa) + 0x7)):
elif ((ebmmu_base + i * 0xa) + 0x6) <= regaddr <= ((ebmmu_base + i * 0xa) + 0x7):
if (self.reg[0x18] & 0x1) == 0x1:
self.reg[regaddr] = val & 0xff
flag = True
elif regaddr == ((0x200 + i * 0xa) + 0x8):
elif regaddr == ((ebmmu_base + i * 0xa) + 0x8):
if (self.reg[0x18] & 0x1) == 0x1:
self.reg[regaddr] = val & 0xff
flag = True
elif regaddr == ((0x200 + i * 0xa) + 0x9):
elif regaddr == ((ebmmu_base + i * 0xa) + 0x9):
if (self.reg[0x18] & 0x1) == 0x1:
self.reg[regaddr] = val & 0xff
flag = True
if flag:
return flag
return False
def __sm_regs_write(self, regaddr, val):
#数据缓冲区描述寄存器组
#sm0 ctrl
if regaddr == 0x300:
self.reg[regaddr] = 0 #val & 0xff
#复位
self.sm0_item_n.value = 0
self.sm0.reset()
elif regaddr == 0x301:
#self.reg[regaddr] = val & 0xff
pass
elif (regaddr >= 0x302) and (regaddr <= 0x303):
if self.reg[0x301] == 0:
self.reg[regaddr] = val & 0xff
#sm1 ctrl
elif regaddr == 0x304:
self.reg[regaddr] = 0 #val & 0xff
#复位
self.sm1_item_n.value = 0
self.sm1.reset()
elif regaddr == 0x305:
pass
elif (regaddr >= 0x306) and (regaddr <= 0x307):
if self.reg[0x305] == 0:
self.reg[regaddr] = val & 0xff
#sm2 ctrl
elif regaddr == 0x308:
self.reg[regaddr] = 0 #val & 0xff
#复位
self.sm2_item_n.value = 0
self.sm2.reset()
elif regaddr == 0x309:
pass
elif (regaddr >= 0x30a) and (regaddr <= 0x30b):
if self.reg[0x309] == 0:
self.reg[regaddr] = val & 0xff
#sm3 ctrl
elif regaddr == 0x30c:
self.reg[regaddr] = 0 #val & 0xff
#复位
self.sm3_item_n.value = 0
self.sm3.reset()
elif regaddr == 0x30d:
pass
elif (regaddr >= 0x30e) and (regaddr <= 0x30f):
if self.reg[0x30d] == 0:
self.reg[regaddr] = val & 0xff
#sm4 ctrl
elif regaddr == 0x310:
self.reg[regaddr] = 0 #val & 0xff
#复位
self.sm4_item_n.value = 0
self.sm4.reset()
elif regaddr == 0x311:
pass
elif (regaddr >= 0x312) and (regaddr <= 0x313):
if self.reg[0x311] == 0:
self.reg[regaddr] = val & 0xff
#sm5 ctrl
elif regaddr == 0x314:
self.reg[regaddr] = 0 #val & 0xff
#复位
self.sm5_item_n.value = 0
self.sm5.reset()
elif regaddr == 0x315:
pass
elif (regaddr >= 0x316) and (regaddr <= 0x317):
if self.reg[0x315] == 0:
self.reg[regaddr] = val & 0xff
#sm6 ctrl
elif regaddr == 0x318:
self.reg[regaddr] = 0 #val & 0xff
#复位
self.sm6_item_n.value = 0
self.sm6.reset()
elif regaddr == 0x319:
pass
elif (regaddr >= 0x31a) and (regaddr <= 0x31b):
if self.reg[0x319] == 0:
self.reg[regaddr] = val & 0xff
#sm7 ctrl
elif regaddr == 0x31c:
self.reg[regaddr] = 0 #val & 0xff
#复位
self.sm7_item_n.value = 0
self.sm7.reset()
elif regaddr == 0x31d:
pass
elif (regaddr >= 0x31e) and (regaddr <= 0x31f):
if self.reg[0x31d] == 0:
self.reg[regaddr] = val & 0xff
#sm0
elif (regaddr >= 0x800) and (regaddr < 0x1000):
self.sm0[regaddr - 0x800] = val
if (regaddr - 0x800) == self.sm0_len.value:
self.sm0.enq_data()
self.sm0_item_n.value = len(self.sm0)
elif (regaddr >= 0x1000) and (regaddr < 0x1800):
self.sm1[regaddr - 0x1000] = val
if (regaddr - 0x1000) == self.sm1_len.value:
self.sm1.enq_data()
self.sm1_item_n.value = len(self.sm1)
elif (regaddr >= 0x1800) and (regaddr < 0x2000):
self.sm2[regaddr - 0x1800] = val
if (regaddr - 0x1800) == self.sm2_len.value:
self.sm2.enq_data()
self.sm2_item_n.value = len(self.sm2)
elif (regaddr >= 0x2000) and (regaddr < 0x2800):
self.sm3[regaddr - 0x2000] = val
if (regaddr - 0x2000) == self.sm3_len.value:
self.sm3.enq_data()
self.sm3_item_n.value = len(self.sm3)
elif (regaddr >= 0x2800) and (regaddr < 0x3000):
self.sm4[regaddr - 0x2800] = val
if (regaddr - 0x2800) == self.sm4_len.value:
self.sm4.enq_data()
self.sm4_item_n.value = len(self.sm4)
elif (regaddr >= 0x3000) and (regaddr < 0x3800):
self.sm5[regaddr - 0x3000] = val
if (regaddr - 0x3000) == self.sm5_len.value:
self.sm5.enq_data()
self.sm5_item_n.value = len(self.sm5)
elif (regaddr >= 0x3800) and (regaddr < 0x4000):
self.sm6[regaddr - 0x3800] = val
if (regaddr - 0x3800) == self.sm6_len.value:
self.sm6.enq_data()
self.sm6_item_n.value = len(self.sm6)
elif (regaddr >= 0x4000) and (regaddr < 0x4800):
self.sm7[regaddr - 0x4000] = val
if (regaddr - 0x4000) == self.sm7_len.value:
self.sm7.enq_data()
self.sm7_item_n.value = len(self.sm7)
else:
return False
continue
return True
return False
def __watch_dog_regs_write(self, regaddr, val):
def __sm_regs_hw(self, regaddr, val):
#数据缓冲区描述寄存器组
'''
self.sm[f'mem{i}'] = MemroyQueueMgr(syncMemNum[i])
self.sm[f'mem{i}_ctrl'] = ArrayUintRef(self.reg, 0x300 + i * 4)
self.sm[f'mem{i}_item_num'] = ArrayUintRef(self.reg, 0x301 + i * 4)
self.sm[f'mem{i}_len'] = ArrayUintRef(self.reg, 0x302 + i * 4, 1)
'''
for i in range(8):
if regaddr == (0x300 + i * 0x4):
self.sm[f'mem{i}_ctrl'].value = 0
#复位
self.sm[f'mem{i}'].reset()
self.sm[f'mem{i}_item_num'].value = 0
elif regaddr == (0x301 + i * 0x4):
pass
elif (0x302 + i * 0x4) <= regaddr <= (0x303 + i * 0x4):
if self.sm[f'mem{i}_item_num'].value == 0:
self.reg[regaddr] = val & 0xff
else:
continue
return True
for i in range(8):
if (0x800 + i * 0x800) <= regaddr < (0x1000 + i * 0x800):
self.sm[f'mem{i}'][regaddr - 0x800 - i * 0x800] = val
if (regaddr - 0x800 - i * 0x800 + 1) == self.sm[f'mem{i}_len'].value:
self.sm[f'mem{i}'].enq_data()
self.sm[f'mem{i}_item_num'].value = len(self.sm[f'mem{i}'])
return True
return False
def __watch_dog_regs_hw(self, regaddr, val):
#看门狗
if (regaddr >= 0x400) and (regaddr <= 0x403):
pass
@@ -836,7 +725,7 @@ class device(object):
return True
def __event_regs_write(self, regaddr, val):
def __event_regs_hw(self, regaddr, val):
if (regaddr >= 0x500) and (regaddr <= 0x501):
pass
elif (regaddr >= 0x502) and (regaddr <= 0x503):