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重新改写一下条件语句，结构上更清晰一些

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This commit is contained in:
bacon
2026-02-26 23:51:42 +08:00
parent 57ab18a492
commit 578d515d3f
1 changed files with 78 additions and 78 deletions
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156
tb/shinTest/shinSim/easybusSim.py
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@@ -327,7 +327,7 @@ class device(object):
# 硬件版本号，写入无效
pass
elif (regaddr >= 0x02) and (regaddr <= 0x07):
elif 0x02 <= regaddr <= 0x07:
# 硬件编码，写入无效
pass
@@ -335,11 +335,11 @@ class device(object):
#硬件接口(0,1,2,3,4,5)
self.reg[regaddr] = val & 0xff
elif (regaddr >= 0x10) and (regaddr <= 0x17):
elif 0x10 <= regaddr <= 0x17:
#硬件唯一编码，写入无效
pass
elif (regaddr >= 0x18) and (regaddr <= 0x19):
elif 0x18 <= regaddr <= 0x19:
#lvds写入锁
if self.role.value == 1:
pass
@@ -358,7 +358,7 @@ class device(object):
def __reset_ctrl_regs_hw(self, regaddr, val):
#EasyBus复位
if (regaddr >= 0x40) and (regaddr <= 0x43):
if 0x40 <= regaddr <= 0x43:
if regaddr == 0x40:
self.reset_0x40 = val & 0x1
elif regaddr == 0x41:
@@ -381,7 +381,7 @@ class device(object):
pass
#交换上下行管脚
elif (regaddr >= 0x4a) and (regaddr <= 0x4b):
elif 0x4a <= regaddr <= 0x4b:
if regaddr == 0x4a:
self.swap_dir_0x4a = val & 0xff
elif regaddr == 0x4b:
@@ -399,7 +399,7 @@ class device(object):
#BIT0:0,选择8b10b编码；1选择4b5b编码
#BIT15-BIT8:key，当KEY = 0x59，且BIT0为1时，4b5b；BIT0为0时，8b10b。
#读取时KEY始终为0。KEY不正确，不响应修改
elif (regaddr >= 0x4c) and (regaddr <= 0x4d):
elif 0x4c <= regaddr <= 0x4d:
if regaddr == 0x4c:
self.code_sel_0x4c = val & 0xff
elif regaddr == 0x4d:
@@ -414,7 +414,7 @@ class device(object):
pass
#CDR参数
elif (regaddr >= 0x4e) and (regaddr <= 0x4f):
elif 0x4e <= regaddr <= 0x4f:
if regaddr == 0x4e:
self.cdr_type_0x4e = val & 0xff
elif regaddr == 0x4f:
@@ -438,23 +438,23 @@ class device(object):
def __int_regs_hw(self, regaddr, val):
#中断使能
if (regaddr >= 0x70) and (regaddr <= 0x73):
if 0x70 <= regaddr <= 0x73:
self.reg[regaddr] = val & 0xff
self.reg[0x73] = self.reg[0x73] | 0x80
#中断状态
elif (regaddr >= 0x74) and (regaddr <= 0x77):
elif 0x74 <= regaddr <= 0x77:
#只读
#warning
pass
#中断状态清除
elif (regaddr >= 0x78) and (regaddr <= 0x7b):
elif 0x78 <= regaddr <= 0x7b:
self.reg[regaddr - 0x4] = (~val) & self.reg[regaddr - 0x4]
self.int_status[regaddr - 0x78] = (~val) & self.int_status[regaddr - 0x78]
#中断模式
elif (regaddr >= 0x7c) and (regaddr <= 0x7d):
elif 0x7c <= regaddr <= 0x7d:
self.reg[regaddr] = val & 0xff
else:
@@ -465,28 +465,28 @@ class device(object):
def __stat_regs_hw(self, regaddr, val):
#统计
#下行接收错误计数器（包括包不完全、CDR、CRC、超时）
if (regaddr >= 0x80) and (regaddr <= 0x81):
if 0x80 <= regaddr <= 0x81:
regaddr[0x80] = 0
regaddr[0x81] = 0
elif (regaddr >= 0x82) and (regaddr <= 0x83):
elif 0x82 <= regaddr <= 0x83:
regaddr[0x82] = 0
regaddr[0x83] = 0
elif (regaddr >= 0x84) and (regaddr <= 0x85):
elif 0x84 <= regaddr <= 0x85:
regaddr[0x84] = 0
regaddr[0x85] = 0
elif (regaddr >= 0x86) and (regaddr <= 0x87):
elif 0x86 <= regaddr <= 0x87:
regaddr[0x86] = 0
regaddr[0x87] = 0
elif (regaddr >= 0x88) and (regaddr <= 0x89):
elif 0x88 <= regaddr <= 0x89:
regaddr[0x88] = 0
regaddr[0x89] = 0
elif (regaddr >= 0x8a) and (regaddr <= 0x8b):
elif 0x8a <= regaddr <= 0x8b:
regaddr[0x8a] = 0
regaddr[0x8b] = 0
elif (regaddr >= 0x8c) and (regaddr <= 0x8f):
elif 0x8c <= regaddr <= 0x8f:
regaddr[0x8c] = 0
regaddr[0x8f] = 0
elif (regaddr >= 0x90) and (regaddr <= 0x97):
elif 0x90 <= regaddr <= 0x97:
regaddr[0x90] = 0
regaddr[0x91] = 0
regaddr[0x92] = 0
@@ -497,28 +497,28 @@ class device(object):
regaddr[0x97] = 0
#上行
elif (regaddr >= 0xa0) and (regaddr <= 0xa1):
elif 0xa0 <= regaddr <= 0xa1:
regaddr[0xa0] = 0
regaddr[0xa1] = 0
elif (regaddr >= 0xa2) and (regaddr <= 0xa3):
elif 0xa2 <= regaddr <= 0xa3:
regaddr[0xa2] = 0
regaddr[0xa3] = 0
elif (regaddr >= 0xa4) and (regaddr <= 0xa5):
elif 0xa4 <= regaddr <= 0xa5:
regaddr[0xa4] = 0
regaddr[0xa5] = 0
elif (regaddr >= 0xa6) and (regaddr <= 0xa7):
elif 0xa6 <= regaddr <= 0xa7:
regaddr[0xa6] = 0
regaddr[0xa7] = 0
elif (regaddr >= 0xa8) and (regaddr <= 0xa9):
elif 0xa8 <= regaddr <= 0xa9:
regaddr[0xa8] = 0
regaddr[0xa9] = 0
elif (regaddr >= 0xaa) and (regaddr <= 0xab):
elif 0xaa <= regaddr <= 0xab:
regaddr[0xaa] = 0
regaddr[0xab] = 0
elif (regaddr >= 0xac) and (regaddr <= 0xaf):
elif 0xac <= regaddr <= 0xaf:
regaddr[0xac] = 0
regaddr[0xad] = 0
elif (regaddr >= 0xb0) and (regaddr <= 0xb7):
elif 0xb0 <= regaddr <= 0xb7:
regaddr[0xb0] = 0
regaddr[0xb1] = 0
regaddr[0xb2] = 0
@@ -536,11 +536,11 @@ class device(object):
def __link_regs_hw(self, regaddr, val):
#两个寄存器都是只读
#链路状态
if (regaddr >= 0xc0) and (regaddr <= 0xc1):
if 0xc0 <= regaddr <= 0xc1:
pass
#右侧设备地址
elif (regaddr >= 0xc2) and (regaddr <= 0xc3):
elif 0xc2 <= regaddr <= 0xc3:
pass
else:
@@ -552,51 +552,51 @@ class device(object):
def __sync_regs_hw(self, regaddr, val):
#同步
#这里注意一个问题，主站是否要考虑lvds侧锁不锁的问题
if (regaddr >= 0x0100) and (regaddr <= 0x107):
if 0x0100 <= regaddr <= 0x107:
pass
elif (regaddr >= 0x0108) and (regaddr <= 0x10f):
elif 0x0108 <= regaddr <= 0x10f:
pass
elif (regaddr >= 0x0110) and (regaddr <= 0x113):
elif 0x0110 <= regaddr <= 0x113:
pass
elif (regaddr >= 0x0114) and (regaddr <= 0x117):
elif 0x0114 <= regaddr <= 0x117:
pass
elif (regaddr >= 0x0118) and (regaddr <= 0x11f):
elif 0x0118 <= regaddr <= 0x11f:
pass
elif (regaddr >= 0x0120) and (regaddr <= 0x121):
elif 0x0120 <= regaddr <= 0x121:
if (self.reg[0x18] & 0x1) == 0x1:
self.reg[regaddr] = val & 0xff
elif (regaddr >= 0x0122) and (regaddr <= 0x123):
elif 0x0122 <= regaddr <= 0x123:
if (self.reg[0x18] & 0x1) == 0x1:
self.reg[regaddr] = val & 0xff
elif (regaddr >= 0x0124) and (regaddr <= 0x125):
elif 0x0124 <= regaddr <= 0x125:
if (self.reg[0x18] & 0x1) == 0x1:
self.reg[regaddr] = val & 0xff
elif (regaddr >= 0x0126) and (regaddr <= 0x127):
elif 0x0126 <= regaddr <= 0x127:
if (self.reg[0x18] & 0x1) == 0x1:
self.reg[regaddr] = val & 0xff
elif (regaddr >= 0x0128) and (regaddr <= 0x129):
elif 0x0128 <= regaddr <= 0x129:
if (self.reg[0x18] & 0x1) == 0x1:
self.reg[regaddr] = val & 0xff
elif (regaddr >= 0x0130) and (regaddr <= 0x137):
elif 0x0130 <= regaddr <= 0x137:
if (self.reg[0x18] & 0x1) == 0x1:
self.reg[regaddr] = val & 0xff
elif (regaddr >= 0x0138) and (regaddr <= 0x13b):
elif 0x0138 <= regaddr <= 0x13b:
if (self.reg[0x18] & 0x1) == 0x1:
self.reg[regaddr] = val & 0xff
elif (regaddr >= 0x013c) and (regaddr <= 0x13f):
elif 0x013c <= regaddr <= 0x13f:
if (self.reg[0x18] & 0x1) == 0x1:
self.reg[regaddr] = val & 0xff
elif (regaddr >= 0x0140) and (regaddr <= 0x143):
elif 0x0140 <= regaddr <= 0x143:
if (self.reg[0x18] & 0x1) == 0x1:
self.reg[regaddr] = val & 0xff
elif (regaddr >= 0x0144) and (regaddr <= 0x147):
elif 0x0144 <= regaddr <= 0x147:
if (self.reg[0x18] & 0x1) == 0x1:
self.reg[regaddr] = val & 0xff
elif (regaddr >= 0x0148) and (regaddr <= 0x14f):
elif 0x0148 <= regaddr <= 0x14f:
if (self.reg[0x18] & 0x1) == 0x1:
self.reg[regaddr] = val & 0xff
else:
@@ -605,7 +605,7 @@ class device(object):
return True
def __custom_def_regs_hw(self, regaddr, val):
if (regaddr >= 0x180) and (regaddr <= 0x1FF):
if 0x180 <= regaddr <= 0x1FF:
self.reg[regaddr] = val & 0xff
else:
return False
@@ -676,49 +676,49 @@ class device(object):
def __watch_dog_regs_hw(self, regaddr, val):
#看门狗
if (regaddr >= 0x400) and (regaddr <= 0x403):
if 0x400 <= regaddr <= 0x403:
pass
elif (regaddr >= 0x404) and (regaddr <= 0x407):
elif 0x404 <= regaddr <= 0x407:
pass
elif (regaddr >= 0x408) and (regaddr <= 0x40B):
elif 0x408 <= regaddr <= 0x40B:
pass
elif (regaddr >= 0x40C) and (regaddr <= 0x40F):
elif 0x40C <= regaddr <= 0x40F:
pass
elif (regaddr >= 0x410) and (regaddr <= 0x413):
elif 0x410 <= regaddr <= 0x413:
pass
elif (regaddr >= 0x414) and (regaddr <= 0x417):
elif 0x414 <= regaddr <= 0x417:
pass
elif (regaddr >= 0x418) and (regaddr <= 0x40B):
elif 0x418 <= regaddr <= 0x40B:
pass
elif (regaddr >= 0x41C) and (regaddr <= 0x41F):
elif 0x41C <= regaddr <= 0x41F:
pass
elif (regaddr >= 0x420) and (regaddr <= 0x423):
elif 0x420 <= regaddr <= 0x423:
pass
elif (regaddr >= 0x424) and (regaddr <= 0x427):
elif 0x424 <= regaddr <= 0x427:
pass
elif (regaddr >= 0x428) and (regaddr <= 0x42B):
elif 0x428 <= regaddr <= 0x42B:
pass
elif (regaddr >= 0x42C) and (regaddr <= 0x42F):
elif 0x42C <= regaddr <= 0x42F:
pass
elif (regaddr >= 0x430) and (regaddr <= 0x433):
elif 0x430 <= regaddr <= 0x433:
pass
elif (regaddr >= 0x434) and (regaddr <= 0x437):
elif 0x434 <= regaddr <= 0x437:
pass
elif (regaddr >= 0x438) and (regaddr <= 0x43B):
elif 0x438 <= regaddr <= 0x43B:
pass
elif (regaddr >= 0x43C) and (regaddr <= 0x43F):
elif 0x43C <= regaddr <= 0x43F:
pass
elif (regaddr >= 0x440) and (regaddr <= 0x443):
elif 0x440 <= regaddr <= 0x443:
pass
elif (regaddr >= 0x444) and (regaddr <= 0x447):
elif 0x444 <= regaddr <= 0x447:
pass
elif (regaddr >= 0x448) and (regaddr <= 0x44B):
elif 0x448 <= regaddr <= 0x44B:
pass
elif (regaddr >= 0x44C) and (regaddr <= 0x44F):
elif 0x44C <= regaddr <= 0x44F:
pass
else:
return False
@@ -726,29 +726,29 @@ class device(object):
return True
def __event_regs_hw(self, regaddr, val):
if (regaddr >= 0x500) and (regaddr <= 0x501):
if 0x500 <= regaddr <= 0x501:
pass
elif (regaddr >= 0x502) and (regaddr <= 0x503):
elif 0x502 <= regaddr <= 0x503:
pass
elif (regaddr >= 0x504) and (regaddr <= 0x505):
elif 0x504 <= regaddr <= 0x505:
pass
elif (regaddr >= 0x506) and (regaddr <= 0x507):
elif 0x506 <= regaddr <= 0x507:
pass
elif (regaddr >= 0x508) and (regaddr <= 0x50F):
elif 0x508 <= regaddr <= 0x50F:
pass
elif (regaddr >= 0x510) and (regaddr <= 0x517):
elif 0x510 <= regaddr <= 0x517:
pass
elif (regaddr >= 0x518) and (regaddr <= 0x51F):
elif 0x518 <= regaddr <= 0x51F:
pass
elif (regaddr >= 0x520) and (regaddr <= 0x527):
elif 0x520 <= regaddr <= 0x527:
pass
elif (regaddr >= 0x528) and (regaddr <= 0x52F):
elif 0x528 <= regaddr <= 0x52F:
pass
elif (regaddr >= 0x530) and (regaddr <= 0x537):
elif 0x530 <= regaddr <= 0x537:
pass
elif (regaddr >= 0x538) and (regaddr <= 0x53F):
elif 0x538 <= regaddr <= 0x53F:
pass
elif (regaddr >= 0x540) and (regaddr <= 0x547):
elif 0x540 <= regaddr <= 0x547:
pass
else:
return False