编译通过。准备测试

src/main/scala/backBoard/shin/ShinMst.scala

@@ -62,6 +62,8 @@ abstract class ShinMstPhyBase extends Module{
   mirrorUp.io.clockA := clock.asBool
   mirrorUp.io.clockB := clock.asBool
 
+  mirrorReg.io.clockA := clock.asBool
+  mirrorReg.io.clockB := clock.asBool
 
   mirrorReg.io.addrB  := DontCare
   mirrorReg.io.datawB := DontCare
@@ -74,7 +76,7 @@ abstract class ShinMstPhyBase extends Module{
 trait ShinMstSend{ this: ShinMstPhyBase =>
 
 
-  val headByte = new Header_Info_Bundle.getWidth()/8
+  val headByte = (new Header_Info_Bundle).getWidth/8
 
   require( headByte == 8 )
 
@@ -111,8 +113,8 @@ trait ShinMstSend{ this: ShinMstPhyBase =>
 
   val isSendTrig: Bool = ~testIOShift(4) & testIOShift(3)
 
-  val isRecvEnd: Bool
+  val isRecvEnd = Wire(Bool())
-  val isTimeout: Bool
+  val isTimeout = Wire(Bool())
 
 
   val sendStateNext = Wire( UInt(3.W) )
@@ -167,15 +169,16 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
 
   val recvLength = recvHeader.asTypeOf(new Header_Info_Bundle).length
 
-  val isRecvEnd = recvStateCurr === 4.U
+  val isRecvEnd: Bool
+  isRecvEnd := recvStateCurr === 4.U
   io.interrupt := recvStateCurr === 4.U
 
 
   recvStateNext := Mux1H(Seq(
     (recvStateCurr === 0.U) -> Mux( isSendTrig, 1.U, 0.U ), //IDLE
     (recvStateCurr === 1.U) -> Mux( cdrIn.io.axis.fire, 2.U, 1.U ), //Arm
-    (recvStateCurr === 2.U) -> Mux( cdrIn.io.axis.fire & recvCnt === ((recvHeader.getWidth()/8-1)*2).U, 3.U, 2.U ), //Header
+    (recvStateCurr === 2.U) -> Mux( cdrIn.io.axis.fire & recvCnt === ((recvHeader.getWidth/8-1)*2).U, 3.U, 2.U ), //Header
-    (recvStateCurr === 3.U) -> Mux( cdrIn.io.axis.fire & recvCnt === (recvHeader.length << 1), 4.U, 3.U ), //payload
+    (recvStateCurr === 3.U) -> Mux( cdrIn.io.axis.fire & recvCnt === (recvLength << 1), 4.U, 3.U ), //payload
     (recvStateCurr === 4.U) -> 0.U, //de-Arm
   ))
 
@@ -192,6 +195,8 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
     recvHeader := Cat( recvHeader.tail(8), cdrIn.io.axis.bits.tdata )
   }
 
+  cdrIn.io.axis.ready := 
+    recvStateCurr === 1.U | recvStateCurr === 2.U | recvStateCurr === 3.U
 
 
 
@@ -222,8 +227,9 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
 
 
 
-
+  val isTimeout: Bool
-  val ( _, isTimeout ) = Counter( Range(0, 20000000), enable = recvStateCurr === 1.U | recvStateCurr === 2.U | recvStateCurr === 3.U, reset = recvStateCurr === 0.U | recvStateCurr === 4.U )
+  isTimeout :=
+    Counter( Range(0, 20000000), enable = recvStateCurr === 1.U | recvStateCurr === 2.U | recvStateCurr === 3.U, reset = recvStateCurr === 0.U | recvStateCurr === 4.U )._2
 
 
 }

src/main/scala/backBoard/shin/ShinSlv.scala

@@ -18,9 +18,6 @@ class ShinSlvIO_Bundle extends Bundle{
     val in   = Input(Bool())
   }
 
-
-
-
   val overCLK = Input(Bool())
 
 }
@@ -48,17 +45,20 @@ abstract class ShinSlvPhyBase extends Module{
   val downRegTemp = Reg(Vec( 32, UInt(8.W) ))
   val upReg       = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))
 
-  val headByte = (new Header_Info_Bundle).getWidth()/8
+  val headByte = (new Header_Info_Bundle).getWidth/8
   require( headByte == 8 )
   require( headByte > 4, "At Least 4 more additional cycles to ensure CRC Failure boardcast to next nodes!\n") 
 
-  val OpInitByte = 1.U
+  val OpInitByte = 1
-  val OpBoardCastByte = 16.U
+  val OpBoardCastByte = 16
-  val OpUniCastByte = 32.U
+  val OpUniCastByte = 32
 
   val maxLocalByte = OpInitByte max OpBoardCastByte max OpUniCastByte
 
-  val isLastDevice: Bool
+  val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + 4 ) )
+  val upStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + maxLocalByte + 4 ) ) //4 is reserve
+
+  val isLastDevice = Wire(Bool())
 
 }
 
@@ -74,26 +74,27 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
   val downOldHead = Reg( new Header_Info_Bundle )
   val downNewHead = Reg( new Header_Info_Bundle )
 
-  val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + 4 ) )
 
-  val downRecvSteteNext = Wire( UInt(3.W) )
+
-  val downRecvStateCurr = RegNext( downRecvSteteNext, 0.U )
+  val downRecvStateNext = Wire( UInt(3.W) )
+  val downRecvStateCurr = RegNext( downRecvStateNext, 0.U )
 
   val downRecvCnt = Reg(UInt(10.W))
 
 
   val downLocalDataByte = Mux1H(Seq(
-    (downOldHead.operator === 0.U) -> OpInitByte,
+    (downOldHead.operator === 0.U) -> OpInitByte.U,
-    (downOldHead.operator === 1.U) -> OpBoardCastByte,
+    (downOldHead.operator === 1.U) -> OpBoardCastByte.U,
-    (downOldHead.operator === 2.U) -> OpUniCastByte,
+    (downOldHead.operator === 2.U) -> OpUniCastByte.U,
   ))
 
   val isDownStreamError = RegInit( false.B )
 
   val downForwardDataByte = downNewHead.length
 
+  val isLastDevice: Bool
 
-  downRecvSteteNext := Mux1H(Seq(
+  downRecvStateNext := Mux1H(Seq(
     (downRecvStateCurr === DownRecvStateIdle ) -> Mux( downStreamCdrIn.io.axis.valid, DownRecvStateOHead, DownRecvStateIdle ),
     (downRecvStateCurr === DownRecvStateOHead) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === ((headByte)-1).U,        DownRecvStateSData, DownRecvStateOHead), DownRecvStateIdle ), DownRecvStateOHead), 
     (downRecvStateCurr === DownRecvStateSData) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === (downLocalDataByte -1.U),  Mux( downRecvCnt === (downOldHead.length - 1.U), DownRecvStateCRC, DownRecvStateFData ), DownRecvStateSData), DownRecvStateIdle ), DownRecvStateSData),
@@ -101,7 +102,7 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
     (downRecvStateCurr === DownRecvStateCRC  ) -> Mux( downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast, DownRecvStateIdle, DownRecvStateCRC ),
   ))
 
-  when( downRecvStateCurr =/= downRecvSteteNext ){
+  when( downRecvStateCurr =/= downRecvStateNext ){
     downRecvCnt := 0.U
   } .elsewhen( downStreamCdrIn.io.axis.fire ){
     downRecvCnt := downRecvCnt + 1.U
@@ -115,7 +116,7 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
 
 
   //---------------
-  val isDownNewHeadCreated = downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateFData //新头是由老头产生，担忧会欠拍
+  val isDownNewHeadCreated = downRecvStateCurr === DownRecvStateSData & downRecvStateNext === DownRecvStateFData //新头是由老头产生，担忧会欠拍
   when( isDownNewHeadCreated ){
     downNewHead.length   := Mux( downOldHead.length >= downLocalDataByte, downOldHead.length - downLocalDataByte, 0.U )
     downNewHead.operator := downOldHead.operator
@@ -140,18 +141,18 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
     ((downRecvStateCurr === DownRecvStateFData) & downStreamFifo.io.enq.ready) |
     (downRecvStateCurr === DownRecvStateCRC  )
 
-  when( downRecvStateCurr === DownRecvStateIdle & downRecvSteteNext === DownRecvStateOHead){
+  when( downRecvStateCurr === DownRecvStateIdle & downRecvStateNext === DownRecvStateOHead){
     isDownStreamError := false.B
   } .elsewhen( downStreamFifo.io.enq.fire & downStreamFifo.io.enq.bits.tuser ){
     isDownStreamError := true.B
     printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
-  } .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvSteteNext === DownRecvStateIdle ){
+  } .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvStateNext === DownRecvStateIdle ){
     isDownStreamError := true.B
     printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
-  } .elsewhen( downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateIdle ){
+  } .elsewhen( downRecvStateCurr === DownRecvStateSData & downRecvStateNext === DownRecvStateIdle ){
     isDownStreamError := true.B
     printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
-  } .elsewhen( downRecvStateCurr === DownRecvStateFData & downRecvSteteNext === DownRecvStateIdle ){
+  } .elsewhen( downRecvStateCurr === DownRecvStateFData & downRecvStateNext === DownRecvStateIdle ){
     isDownStreamError := true.B
     printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
   } .elsewhen( downRecvStateCurr === DownRecvStateCRC & (downRecvCnt > 3.U | (downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast & downRecvCnt < 3.U)) ){
@@ -180,6 +181,12 @@ trait ShinSlvPhyDownStreamSend{ this: ShinSlvPhyBase =>
 
   val downSendCnt = Reg(UInt(10.W))
 
+  val isDownNewHeadCreated: Bool
+  val isLastDevice: Bool
+  val downForwardDataByte: UInt
+  val downNewHead: Header_Info_Bundle
+  val isDownStreamError: Bool
+
 
   val downSendSteteNext = Wire( UInt(3.W) )
   val downSendStateCurr = RegNext( downSendSteteNext, 0.U )
@@ -233,13 +240,13 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
   val upOldHead = Reg( new Header_Info_Bundle )
   val upNewHead = Reg( new Header_Info_Bundle )
 
-  val upStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + maxLocalByte + 4 ) ) //4 is reserve
 
   val upRecvSteteNext = Wire( UInt(3.W) )
   val upRecvStateCurr = RegNext( upRecvSteteNext, 0.U )
 
   val upRecvCnt = Reg(UInt(10.W))
-  val upSendCnt = Reg(UInt(10.W))
+
+  val isLastDevice: Bool
 
   upRecvSteteNext := Mux1H(Seq(
     (upRecvStateCurr === UpRecvStateIdle ) -> Mux( upStreamCdrIn.io.axis.valid, UpRecvStateOHead, UpRecvStateIdle ),
@@ -262,7 +269,7 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
   //---------------
 
   when( (upRecvStateCurr === UpRecvStateOHead & upStreamCdrIn.io.axis.fire) ){
-    upOldHead := Cat( upOldHead.asUInt.tail(8), upStreamCdrIn.io.axis.tdata ).asTypeOf(Header_Info_Bundle)
+    upOldHead := Cat( upOldHead.asUInt.tail(8), upStreamCdrIn.io.axis.bits.tdata ).asTypeOf(new Header_Info_Bundle)
   } .elsewhen( isLastDownStreamEnd ){
     upOldHead.operator := downOldHead.operator
     upOldHead.length   := 0.U
@@ -278,9 +285,9 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
 
 
  val upLocalDataByte = Mux1H(Seq(
-    (upOldHead.operator === 0.U) -> OpInitByte,
+    (upOldHead.operator === 0.U) -> OpInitByte.U,
-    (upOldHead.operator === 1.U) -> OpBoardCastByte,
+    (upOldHead.operator === 1.U) -> OpBoardCastByte.U,
-    (upOldHead.operator === 2.U) -> OpUniCastByte,
+    (upOldHead.operator === 2.U) -> OpUniCastByte.U,
   ))
 
 
@@ -352,17 +359,26 @@ trait ShinSlvPhyUpStreamSend{ this: ShinSlvPhyDownStream =>
 
 
 
-  val upSendSteteNext = Wire( UInt(3.W) )
+  val upSendStateNext = Wire( UInt(3.W) )
   val upSendStateCurr = RegNext( downSendSteteNext, 0.U )
 
-  upSendSteteNext := Mux1H(Seq(
+  val upSendCnt = Reg(UInt(10.W))
+
+  val isUpNewHeadCreated: Bool
+  val upLocalDataByte: UInt
+  val isLastDevice: Bool
+  val upForwardDataByte: UInt
+  val upNewHead: Header_Info_Bundle
+  val isUpStreamError: Bool
+
+  upSendStateNext := Mux1H(Seq(
     ( upSendStateCurr === UpSendStateIdle  ) -> Mux( isUpNewHeadCreated, UpSendStateNHead, UpSendStateIdle ),
     ( upSendStateCurr === UpSendStateNHead ) -> Mux( upSendCnt === ((headByte)-1).U & upStreamCdrOut.io.axis.fire,          UpSendStateLData, UpSendStateNHead),
     ( upSendStateCurr === UpSendStateLData ) -> Mux( upSendCnt === (upLocalDataByte   - 1.U) & upStreamCdrOut.io.axis.fire, Mux( isLastDevice, UpSendStateIdle, UpSendStateFData), UpSendStateLData),
     ( upSendStateCurr === UpSendStateFData ) -> Mux( upSendCnt === (upForwardDataByte - 1.U) & upStreamCdrOut.io.axis.fire, UpSendStateIdle,  UpSendStateFData),
   ))
 
-  when( upSendStateCurr =/= upSendSteteNext ){
+  when( upSendStateCurr =/= upSendStateNext ){
     upSendCnt := 0.U
   } .elsewhen( upStreamCdrOut.io.axis.fire ){
     upSendCnt := upSendCnt + 1.U
@@ -375,14 +391,14 @@ trait ShinSlvPhyUpStreamSend{ this: ShinSlvPhyDownStream =>
     upSendStateCurr === UpSendStateNHead | upSendStateCurr === UpSendStateLData | upSendStateCurr === UpSendStateFData
 
   upStreamCdrOut.io.axis.bits.tdata := Mux1H(Seq(
-    ( upSendStateCurr === UpSendStateNHead ) -> (upewHead.asUInt << (upSendCnt << 3)).head(8),
+    ( upSendStateCurr === UpSendStateNHead ) -> (upNewHead.asUInt << (upSendCnt << 3)).head(8),
     ( upSendStateCurr === UpSendStateLData ) -> upReg(upSendCnt),
     ( upSendStateCurr === UpSendStateFData ) -> upStreamFifo.io.deq.bits.tdata,
   ))
 
   upStreamCdrOut.io.axis.bits.tlast := ( upSendStateCurr === UpSendStateFData ) & upStreamFifo.io.deq.bits.tlast
 
-  downStreamCdrOut.io.axis.bits.tuser :=
+  upStreamCdrOut.io.axis.bits.tuser :=
     (( upSendStateCurr === UpSendStateFData ) & upStreamFifo.io.deq.bits.tuser ) |
     isUpStreamError
 
@@ -405,8 +421,8 @@ trait ShinSlvPhyUpStreamSend{ this: ShinSlvPhyDownStream =>
 
 
 abstract class ShinSlvLinkBase extends ShinSlvPhyDownStream
-with ShinSlvPhyDownStream
+with ShinSlvPhyUpStreamRecv
-with ShinSlvPhyUpStream
+with ShinSlvPhyUpStreamSend
 // with ShinSlvPhyCloseLoop
 {
 
@@ -432,7 +448,7 @@ trait ShinSlvLinkInit{ this: ShinSlvLinkBase =>
   val slvNum = Reg(UInt(7.W))
   val slvRTC = Reg(UInt(64.W))
 
-  val isLastDevice = isLastInit | io.isLast
+  isLastDevice := isLastInit | io.isLast
 
   val isLegalInitDownHead = 
     downOldHead.operator === 0.U & 
@@ -441,6 +457,12 @@ trait ShinSlvLinkInit{ this: ShinSlvLinkBase =>
   val isDownUpdate = RegInit(false.B)
   val isUpUpdate   = RegInit(false.B)
 
+  val isLastDownStreamEnd: Bool
+  val isUpStreamEnd: Bool
+  val upOldHead: Header_Info_Bundle
+  val isUpNewHeadCreated: Bool
+
+
   when( (isDownNewHeadCreated | isLastDownStreamEnd) & isLegalInitDownHead ){
     slvID := 64.U - (downOldHead.length >> 3)
     isDownUpdate := true.B