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编译通过。准备测试

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This commit is contained in:
RuigeLee
2024-10-16 10:49:06 +08:00
parent a44cae1ec3
commit 55f016d866
2 changed files with 71 additions and 43 deletions
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22
src/main/scala/backBoard/shin/ShinMst.scala
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@@ -62,6 +62,8 @@ abstract class ShinMstPhyBase extends Module{
mirrorUp.io.clockA := clock.asBool
mirrorUp.io.clockB := clock.asBool
mirrorReg.io.clockA := clock.asBool
mirrorReg.io.clockB := clock.asBool
mirrorReg.io.addrB := DontCare
mirrorReg.io.datawB := DontCare
@@ -74,7 +76,7 @@ abstract class ShinMstPhyBase extends Module{
trait ShinMstSend{ this: ShinMstPhyBase =>
val headByte = new Header_Info_Bundle.getWidth()/8
val headByte = (new Header_Info_Bundle).getWidth/8
require( headByte == 8 )
@@ -111,8 +113,8 @@ trait ShinMstSend{ this: ShinMstPhyBase =>
val isSendTrig: Bool = ~testIOShift(4) & testIOShift(3)
val isRecvEnd: Bool
val isTimeout: Bool
val isRecvEnd = Wire(Bool())
val isTimeout = Wire(Bool())
val sendStateNext = Wire( UInt(3.W) )
@@ -167,15 +169,16 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
val recvLength = recvHeader.asTypeOf(new Header_Info_Bundle).length
val isRecvEnd = recvStateCurr === 4.U
val isRecvEnd: Bool
isRecvEnd := recvStateCurr === 4.U
io.interrupt := recvStateCurr === 4.U
recvStateNext := Mux1H(Seq(
(recvStateCurr === 0.U) -> Mux( isSendTrig, 1.U, 0.U ), //IDLE
(recvStateCurr === 1.U) -> Mux( cdrIn.io.axis.fire, 2.U, 1.U ), //Arm
(recvStateCurr === 2.U) -> Mux( cdrIn.io.axis.fire & recvCnt === ((recvHeader.getWidth()/8-1)*2).U, 3.U, 2.U ), //Header
(recvStateCurr === 3.U) -> Mux( cdrIn.io.axis.fire & recvCnt === (recvHeader.length << 1), 4.U, 3.U ), //payload
(recvStateCurr === 2.U) -> Mux( cdrIn.io.axis.fire & recvCnt === ((recvHeader.getWidth/8-1)*2).U, 3.U, 2.U ), //Header
(recvStateCurr === 3.U) -> Mux( cdrIn.io.axis.fire & recvCnt === (recvLength << 1), 4.U, 3.U ), //payload
(recvStateCurr === 4.U) -> 0.U, //de-Arm
))
@@ -192,6 +195,8 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
recvHeader := Cat( recvHeader.tail(8), cdrIn.io.axis.bits.tdata )
}
cdrIn.io.axis.ready :=
recvStateCurr === 1.U | recvStateCurr === 2.U | recvStateCurr === 3.U
@@ -222,8 +227,9 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
val ( _, isTimeout ) = Counter( Range(0, 20000000), enable = recvStateCurr === 1.U | recvStateCurr === 2.U | recvStateCurr === 3.U, reset = recvStateCurr === 0.U | recvStateCurr === 4.U )
val isTimeout: Bool
isTimeout :=
Counter( Range(0, 20000000), enable = recvStateCurr === 1.U | recvStateCurr === 2.U | recvStateCurr === 3.U, reset = recvStateCurr === 0.U | recvStateCurr === 4.U )._2
}