编译通过。准备测试
This commit is contained in:
RuigeLee
@@ -62,6 +62,8 @@ abstract class ShinMstPhyBase extends Module{
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mirrorUp.io.clockA := clock.asBool
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mirrorUp.io.clockB := clock.asBool
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mirrorReg.io.clockA := clock.asBool
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mirrorReg.io.clockB := clock.asBool
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mirrorReg.io.addrB := DontCare
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mirrorReg.io.datawB := DontCare
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@@ -74,7 +76,7 @@ abstract class ShinMstPhyBase extends Module{
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trait ShinMstSend{ this: ShinMstPhyBase =>
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val headByte = new Header_Info_Bundle.getWidth()/8
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val headByte = (new Header_Info_Bundle).getWidth/8
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require( headByte == 8 )
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@@ -111,8 +113,8 @@ trait ShinMstSend{ this: ShinMstPhyBase =>
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val isSendTrig: Bool = ~testIOShift(4) & testIOShift(3)
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val isRecvEnd: Bool
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val isTimeout: Bool
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val isRecvEnd = Wire(Bool())
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val isTimeout = Wire(Bool())
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val sendStateNext = Wire( UInt(3.W) )
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@@ -167,15 +169,16 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
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val recvLength = recvHeader.asTypeOf(new Header_Info_Bundle).length
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val isRecvEnd = recvStateCurr === 4.U
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val isRecvEnd: Bool
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isRecvEnd := recvStateCurr === 4.U
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io.interrupt := recvStateCurr === 4.U
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recvStateNext := Mux1H(Seq(
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(recvStateCurr === 0.U) -> Mux( isSendTrig, 1.U, 0.U ), //IDLE
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(recvStateCurr === 1.U) -> Mux( cdrIn.io.axis.fire, 2.U, 1.U ), //Arm
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(recvStateCurr === 2.U) -> Mux( cdrIn.io.axis.fire & recvCnt === ((recvHeader.getWidth()/8-1)*2).U, 3.U, 2.U ), //Header
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(recvStateCurr === 3.U) -> Mux( cdrIn.io.axis.fire & recvCnt === (recvHeader.length << 1), 4.U, 3.U ), //payload
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(recvStateCurr === 2.U) -> Mux( cdrIn.io.axis.fire & recvCnt === ((recvHeader.getWidth/8-1)*2).U, 3.U, 2.U ), //Header
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(recvStateCurr === 3.U) -> Mux( cdrIn.io.axis.fire & recvCnt === (recvLength << 1), 4.U, 3.U ), //payload
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(recvStateCurr === 4.U) -> 0.U, //de-Arm
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))
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@@ -192,6 +195,8 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
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recvHeader := Cat( recvHeader.tail(8), cdrIn.io.axis.bits.tdata )
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}
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cdrIn.io.axis.ready :=
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recvStateCurr === 1.U | recvStateCurr === 2.U | recvStateCurr === 3.U
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@@ -222,8 +227,9 @@ trait ShinMstRecv{ this: ShinMstPhyBase =>
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val ( _, isTimeout ) = Counter( Range(0, 20000000), enable = recvStateCurr === 1.U | recvStateCurr === 2.U | recvStateCurr === 3.U, reset = recvStateCurr === 0.U | recvStateCurr === 4.U )
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val isTimeout: Bool
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isTimeout :=
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Counter( Range(0, 20000000), enable = recvStateCurr === 1.U | recvStateCurr === 2.U | recvStateCurr === 3.U, reset = recvStateCurr === 0.U | recvStateCurr === 4.U )._2
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}
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@@ -18,9 +18,6 @@ class ShinSlvIO_Bundle extends Bundle{
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val in = Input(Bool())
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}
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val overCLK = Input(Bool())
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}
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@@ -48,17 +45,20 @@ abstract class ShinSlvPhyBase extends Module{
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val downRegTemp = Reg(Vec( 32, UInt(8.W) ))
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val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))
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val headByte = (new Header_Info_Bundle).getWidth()/8
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val headByte = (new Header_Info_Bundle).getWidth/8
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require( headByte == 8 )
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require( headByte > 4, "At Least 4 more additional cycles to ensure CRC Failure boardcast to next nodes!\n")
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val OpInitByte = 1.U
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val OpBoardCastByte = 16.U
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val OpUniCastByte = 32.U
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val OpInitByte = 1
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val OpBoardCastByte = 16
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val OpUniCastByte = 32
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val maxLocalByte = OpInitByte max OpBoardCastByte max OpUniCastByte
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val isLastDevice: Bool
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val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + 4 ) )
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val upStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + maxLocalByte + 4 ) ) //4 is reserve
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val isLastDevice = Wire(Bool())
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}
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@@ -74,26 +74,27 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
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val downOldHead = Reg( new Header_Info_Bundle )
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val downNewHead = Reg( new Header_Info_Bundle )
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val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + 4 ) )
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val downRecvSteteNext = Wire( UInt(3.W) )
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val downRecvStateCurr = RegNext( downRecvSteteNext, 0.U )
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val downRecvStateNext = Wire( UInt(3.W) )
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val downRecvStateCurr = RegNext( downRecvStateNext, 0.U )
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val downRecvCnt = Reg(UInt(10.W))
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val downLocalDataByte = Mux1H(Seq(
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(downOldHead.operator === 0.U) -> OpInitByte,
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(downOldHead.operator === 1.U) -> OpBoardCastByte,
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(downOldHead.operator === 2.U) -> OpUniCastByte,
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(downOldHead.operator === 0.U) -> OpInitByte.U,
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(downOldHead.operator === 1.U) -> OpBoardCastByte.U,
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(downOldHead.operator === 2.U) -> OpUniCastByte.U,
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))
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val isDownStreamError = RegInit( false.B )
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val downForwardDataByte = downNewHead.length
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val isLastDevice: Bool
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downRecvSteteNext := Mux1H(Seq(
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downRecvStateNext := Mux1H(Seq(
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(downRecvStateCurr === DownRecvStateIdle ) -> Mux( downStreamCdrIn.io.axis.valid, DownRecvStateOHead, DownRecvStateIdle ),
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(downRecvStateCurr === DownRecvStateOHead) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === ((headByte)-1).U, DownRecvStateSData, DownRecvStateOHead), DownRecvStateIdle ), DownRecvStateOHead),
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(downRecvStateCurr === DownRecvStateSData) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === (downLocalDataByte -1.U), Mux( downRecvCnt === (downOldHead.length - 1.U), DownRecvStateCRC, DownRecvStateFData ), DownRecvStateSData), DownRecvStateIdle ), DownRecvStateSData),
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@@ -101,7 +102,7 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
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(downRecvStateCurr === DownRecvStateCRC ) -> Mux( downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast, DownRecvStateIdle, DownRecvStateCRC ),
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))
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when( downRecvStateCurr =/= downRecvSteteNext ){
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when( downRecvStateCurr =/= downRecvStateNext ){
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downRecvCnt := 0.U
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} .elsewhen( downStreamCdrIn.io.axis.fire ){
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downRecvCnt := downRecvCnt + 1.U
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@@ -115,7 +116,7 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
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//---------------
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val isDownNewHeadCreated = downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateFData //新头是由老头产生，担忧会欠拍
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val isDownNewHeadCreated = downRecvStateCurr === DownRecvStateSData & downRecvStateNext === DownRecvStateFData //新头是由老头产生，担忧会欠拍
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when( isDownNewHeadCreated ){
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downNewHead.length := Mux( downOldHead.length >= downLocalDataByte, downOldHead.length - downLocalDataByte, 0.U )
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downNewHead.operator := downOldHead.operator
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@@ -140,18 +141,18 @@ trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
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((downRecvStateCurr === DownRecvStateFData) & downStreamFifo.io.enq.ready) |
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(downRecvStateCurr === DownRecvStateCRC )
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when( downRecvStateCurr === DownRecvStateIdle & downRecvSteteNext === DownRecvStateOHead){
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when( downRecvStateCurr === DownRecvStateIdle & downRecvStateNext === DownRecvStateOHead){
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isDownStreamError := false.B
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} .elsewhen( downStreamFifo.io.enq.fire & downStreamFifo.io.enq.bits.tuser ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvSteteNext === DownRecvStateIdle ){
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} .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvStateNext === DownRecvStateIdle ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateIdle ){
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} .elsewhen( downRecvStateCurr === DownRecvStateSData & downRecvStateNext === DownRecvStateIdle ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateFData & downRecvSteteNext === DownRecvStateIdle ){
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} .elsewhen( downRecvStateCurr === DownRecvStateFData & downRecvStateNext === DownRecvStateIdle ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateCRC & (downRecvCnt > 3.U | (downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast & downRecvCnt < 3.U)) ){
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@@ -180,6 +181,12 @@ trait ShinSlvPhyDownStreamSend{ this: ShinSlvPhyBase =>
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val downSendCnt = Reg(UInt(10.W))
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val isDownNewHeadCreated: Bool
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val isLastDevice: Bool
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val downForwardDataByte: UInt
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val downNewHead: Header_Info_Bundle
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val isDownStreamError: Bool
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val downSendSteteNext = Wire( UInt(3.W) )
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val downSendStateCurr = RegNext( downSendSteteNext, 0.U )
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@@ -233,13 +240,13 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
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val upOldHead = Reg( new Header_Info_Bundle )
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val upNewHead = Reg( new Header_Info_Bundle )
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val upStreamFifo = Module( new Queue( new AXIS_Bundle(8), headByte + maxLocalByte + 4 ) ) //4 is reserve
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val upRecvSteteNext = Wire( UInt(3.W) )
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val upRecvStateCurr = RegNext( upRecvSteteNext, 0.U )
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val upRecvCnt = Reg(UInt(10.W))
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val upSendCnt = Reg(UInt(10.W))
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val isLastDevice: Bool
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upRecvSteteNext := Mux1H(Seq(
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(upRecvStateCurr === UpRecvStateIdle ) -> Mux( upStreamCdrIn.io.axis.valid, UpRecvStateOHead, UpRecvStateIdle ),
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@@ -262,7 +269,7 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
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//---------------
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when( (upRecvStateCurr === UpRecvStateOHead & upStreamCdrIn.io.axis.fire) ){
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upOldHead := Cat( upOldHead.asUInt.tail(8), upStreamCdrIn.io.axis.tdata ).asTypeOf(Header_Info_Bundle)
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upOldHead := Cat( upOldHead.asUInt.tail(8), upStreamCdrIn.io.axis.bits.tdata ).asTypeOf(new Header_Info_Bundle)
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} .elsewhen( isLastDownStreamEnd ){
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upOldHead.operator := downOldHead.operator
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upOldHead.length := 0.U
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@@ -278,9 +285,9 @@ trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
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val upLocalDataByte = Mux1H(Seq(
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(upOldHead.operator === 0.U) -> OpInitByte,
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(upOldHead.operator === 1.U) -> OpBoardCastByte,
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(upOldHead.operator === 2.U) -> OpUniCastByte,
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(upOldHead.operator === 0.U) -> OpInitByte.U,
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(upOldHead.operator === 1.U) -> OpBoardCastByte.U,
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(upOldHead.operator === 2.U) -> OpUniCastByte.U,
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))
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@@ -352,17 +359,26 @@ trait ShinSlvPhyUpStreamSend{ this: ShinSlvPhyDownStream =>
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val upSendSteteNext = Wire( UInt(3.W) )
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val upSendStateNext = Wire( UInt(3.W) )
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val upSendStateCurr = RegNext( downSendSteteNext, 0.U )
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upSendSteteNext := Mux1H(Seq(
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val upSendCnt = Reg(UInt(10.W))
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val isUpNewHeadCreated: Bool
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val upLocalDataByte: UInt
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val isLastDevice: Bool
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val upForwardDataByte: UInt
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val upNewHead: Header_Info_Bundle
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val isUpStreamError: Bool
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upSendStateNext := Mux1H(Seq(
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( upSendStateCurr === UpSendStateIdle ) -> Mux( isUpNewHeadCreated, UpSendStateNHead, UpSendStateIdle ),
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( upSendStateCurr === UpSendStateNHead ) -> Mux( upSendCnt === ((headByte)-1).U & upStreamCdrOut.io.axis.fire, UpSendStateLData, UpSendStateNHead),
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( upSendStateCurr === UpSendStateLData ) -> Mux( upSendCnt === (upLocalDataByte - 1.U) & upStreamCdrOut.io.axis.fire, Mux( isLastDevice, UpSendStateIdle, UpSendStateFData), UpSendStateLData),
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( upSendStateCurr === UpSendStateFData ) -> Mux( upSendCnt === (upForwardDataByte - 1.U) & upStreamCdrOut.io.axis.fire, UpSendStateIdle, UpSendStateFData),
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))
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when( upSendStateCurr =/= upSendSteteNext ){
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when( upSendStateCurr =/= upSendStateNext ){
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upSendCnt := 0.U
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} .elsewhen( upStreamCdrOut.io.axis.fire ){
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upSendCnt := upSendCnt + 1.U
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@@ -375,14 +391,14 @@ trait ShinSlvPhyUpStreamSend{ this: ShinSlvPhyDownStream =>
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upSendStateCurr === UpSendStateNHead | upSendStateCurr === UpSendStateLData | upSendStateCurr === UpSendStateFData
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upStreamCdrOut.io.axis.bits.tdata := Mux1H(Seq(
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( upSendStateCurr === UpSendStateNHead ) -> (upewHead.asUInt << (upSendCnt << 3)).head(8),
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( upSendStateCurr === UpSendStateNHead ) -> (upNewHead.asUInt << (upSendCnt << 3)).head(8),
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( upSendStateCurr === UpSendStateLData ) -> upReg(upSendCnt),
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( upSendStateCurr === UpSendStateFData ) -> upStreamFifo.io.deq.bits.tdata,
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))
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upStreamCdrOut.io.axis.bits.tlast := ( upSendStateCurr === UpSendStateFData ) & upStreamFifo.io.deq.bits.tlast
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downStreamCdrOut.io.axis.bits.tuser :=
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upStreamCdrOut.io.axis.bits.tuser :=
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(( upSendStateCurr === UpSendStateFData ) & upStreamFifo.io.deq.bits.tuser ) |
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isUpStreamError
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@@ -405,8 +421,8 @@ trait ShinSlvPhyUpStreamSend{ this: ShinSlvPhyDownStream =>
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abstract class ShinSlvLinkBase extends ShinSlvPhyDownStream
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with ShinSlvPhyDownStream
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with ShinSlvPhyUpStream
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with ShinSlvPhyUpStreamRecv
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with ShinSlvPhyUpStreamSend
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// with ShinSlvPhyCloseLoop
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{
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@@ -432,7 +448,7 @@ trait ShinSlvLinkInit{ this: ShinSlvLinkBase =>
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val slvNum = Reg(UInt(7.W))
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val slvRTC = Reg(UInt(64.W))
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val isLastDevice = isLastInit | io.isLast
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isLastDevice := isLastInit | io.isLast
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val isLegalInitDownHead =
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downOldHead.operator === 0.U &
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@@ -441,6 +457,12 @@ trait ShinSlvLinkInit{ this: ShinSlvLinkBase =>
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val isDownUpdate = RegInit(false.B)
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val isUpUpdate = RegInit(false.B)
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val isLastDownStreamEnd: Bool
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val isUpStreamEnd: Bool
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val upOldHead: Header_Info_Bundle
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val isUpNewHeadCreated: Bool
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when( (isDownNewHeadCreated | isLastDownStreamEnd) & isLegalInitDownHead ){
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slvID := 64.U - (downOldHead.length >> 3)
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isDownUpdate := true.B
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Block a user