Tx尝试统一接口,失败
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@@ -736,14 +736,30 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
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val macTileLinkTx = withClockAndReset( io.mii.mtx_clk_pad_i.asClock, io.asyncReset ) (Module(new MacTileLinkTx))
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val txReq_ToAsync = Wire(new AsyncBundle(UInt(8.W)))
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// val txResp_ToAsync = Wire(new AsyncBundle(Bool()))
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// val fateTxRespPort = Wire( Flipped(Decoupled(Bool())) )
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// fateTxReqPort.ready := true.B
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// wishbone.io.txResp <> FromAsyncBundle( txResp_ToAsync )
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txReq_ToAsync <> ToAsyncBundle( wishbone.io.txReq )
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withClockAndReset(io.mii.mtx_clk_pad_i.asClock, io.asyncReset) {
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// txResp_ToAsync <> ToAsyncBundle( macTileLinkTx.io.txResp )
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macTileLinkTx.io.txReq <> FromAsyncBundle( txReq_ToAsync )
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}
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// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
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val ReadTxDataFromFifo_sync = ShiftRegister( macTileLinkTx.io.ReadTxDataFromFifo_tck, 2, false.B, true.B)
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wishbone.io.ReadTxDataFromFifo_sync := ReadTxDataFromFifo_sync
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// val ReadTxDataFromFifo_sync = ShiftRegister( macTileLinkTx.io.ReadTxDataFromFifo_tck, 2, false.B, true.B)
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// wishbone.io.ReadTxDataFromFifo_sync := ReadTxDataFromFifo_sync
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withClockAndReset( io.mii.mtx_clk_pad_i.asClock, io.asyncReset ){
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macTileLinkTx.io.BlockingTxStatusWrite_sync := ShiftRegister( wishbone.io.BlockingTxStatusWrite, 2, false.B, true.B)
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macTileLinkTx.io.TxStartFrm_sync := ShiftRegister( wishbone.io.TxStartFrm_wb, 2, false.B, true.B ) // Synchronizing TxStartFrm_wb to MTxClk
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macTileLinkTx.io.ReadTxDataFromFifo_syncb := ShiftRegister( ReadTxDataFromFifo_sync, 2, false.B, true.B)
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// macTileLinkTx.io.ReadTxDataFromFifo_syncb := ShiftRegister( ReadTxDataFromFifo_sync, 2, false.B, true.B)
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}
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@@ -755,7 +771,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
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TxData := macTileLinkTx.io.TxData
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macTileLinkTx.io.TxData_wb := wishbone.io.TxData_wb
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// macTileLinkTx.io.TxData_wb := wishbone.io.TxData_wb
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macTileLinkTx.io.TxEndFrm_wb := wishbone.io.TxEndFrm_wb
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wishbone.io.TxUsedData := TxUsedData
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