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Tx尝试统一接口，失败

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This commit is contained in:
RuigeLee
2023-10-23 23:36:01 +08:00
parent faa46be8ef
commit 54991d8cb5
3 changed files with 59 additions and 21 deletions
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24
src/main/scala/Switch/mac/MAC.scala
View File

@@ -736,14 +736,30 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
val macTileLinkTx = withClockAndReset( io.mii.mtx_clk_pad_i.asClock, io.asyncReset ) (Module(new MacTileLinkTx))
val txReq_ToAsync = Wire(new AsyncBundle(UInt(8.W)))
// val txResp_ToAsync = Wire(new AsyncBundle(Bool()))
// val fateTxRespPort = Wire( Flipped(Decoupled(Bool())) )
// fateTxReqPort.ready := true.B
// wishbone.io.txResp <> FromAsyncBundle( txResp_ToAsync )
txReq_ToAsync <> ToAsyncBundle( wishbone.io.txReq )
withClockAndReset(io.mii.mtx_clk_pad_i.asClock, io.asyncReset) {
// txResp_ToAsync <> ToAsyncBundle( macTileLinkTx.io.txResp )
macTileLinkTx.io.txReq <> FromAsyncBundle( txReq_ToAsync )
}
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
val ReadTxDataFromFifo_sync = ShiftRegister( macTileLinkTx.io.ReadTxDataFromFifo_tck, 2, false.B, true.B)
wishbone.io.ReadTxDataFromFifo_sync := ReadTxDataFromFifo_sync
// val ReadTxDataFromFifo_sync = ShiftRegister( macTileLinkTx.io.ReadTxDataFromFifo_tck, 2, false.B, true.B)
// wishbone.io.ReadTxDataFromFifo_sync := ReadTxDataFromFifo_sync
withClockAndReset( io.mii.mtx_clk_pad_i.asClock, io.asyncReset ){
macTileLinkTx.io.BlockingTxStatusWrite_sync := ShiftRegister( wishbone.io.BlockingTxStatusWrite, 2, false.B, true.B)
macTileLinkTx.io.TxStartFrm_sync := ShiftRegister( wishbone.io.TxStartFrm_wb, 2, false.B, true.B ) // Synchronizing TxStartFrm_wb to MTxClk
macTileLinkTx.io.ReadTxDataFromFifo_syncb := ShiftRegister( ReadTxDataFromFifo_sync, 2, false.B, true.B)
// macTileLinkTx.io.ReadTxDataFromFifo_syncb := ShiftRegister( ReadTxDataFromFifo_sync, 2, false.B, true.B)
}
@@ -755,7 +771,7 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
TxData := macTileLinkTx.io.TxData
macTileLinkTx.io.TxData_wb := wishbone.io.TxData_wb
// macTileLinkTx.io.TxData_wb := wishbone.io.TxData_wb
macTileLinkTx.io.TxEndFrm_wb := wishbone.io.TxEndFrm_wb
wishbone.io.TxUsedData := TxUsedData

40
src/main/scala/Switch/mac/MacTileLinkTx.scala
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@@ -5,6 +5,12 @@ import chisel3.util._
class MacTileLinkTxIO extends Bundle{
val txReq = Flipped(Decoupled(UInt(8.W)))
// val txResp = Decoupled()
val RstDeferLatched = Output(Bool())
val BlockingTxStatusWrite_sync = Input(Bool())
val TxStartFrm_sync = Input(Bool())
@@ -18,11 +24,11 @@ class MacTileLinkTxIO extends Bundle{
val TxAbort = Input(Bool()) // Transmit packet abort
val TxDone = Input(Bool()) // Transmission ended
val ReadTxDataFromFifo_tck = Output(Bool())
val ReadTxDataFromFifo_syncb = Input(Bool())
// val ReadTxDataFromFifo_tck = Output(Bool())
// val ReadTxDataFromFifo_syncb = Input(Bool())
val TxEndFrm_wb = Input(Bool())
val TxData_wb = Input(UInt(8.W))
// val TxData_wb = Input(UInt(8.W))
}
@@ -38,7 +44,9 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
val TxEndFrm = RegInit(false.B); io.TxEndFrm := TxEndFrm
val TxData = RegInit(0.U(8.W)); io.TxData := TxData
val LastWord = RegInit(false.B)
val ReadTxDataFromFifo_tck = RegInit(false.B); io.ReadTxDataFromFifo_tck := ReadTxDataFromFifo_tck
val ReadTxDataFromFifo_tck = RegInit(false.B);
// io.ReadTxDataFromFifo_tck := ReadTxDataFromFifo_tck
// Generating delayed signals
val TxAbort_q = RegNext( io.TxAbort, false.B)
@@ -75,15 +83,25 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
when(
// when(
// io.TxStartFrm_sync & ~TxStartFrm |
// io.TxUsedData & Flop & ~LastWord |
// TxStartFrm & io.TxUsedData & Flop ){
// ReadTxDataFromFifo_tck := true.B
// // TxData := io.TxData_wb( 7, 0)
//
// } .elsewhen(io.ReadTxDataFromFifo_syncb & ~RegNext(io.ReadTxDataFromFifo_syncb, false.B)){
// ReadTxDataFromFifo_tck := false.B
// }
io.txReq.ready :=
io.TxStartFrm_sync & ~TxStartFrm |
io.TxUsedData & Flop & ~LastWord |
TxStartFrm & io.TxUsedData & Flop ){
ReadTxDataFromFifo_tck := true.B
TxData := io.TxData_wb( 7, 0)
} .elsewhen(io.ReadTxDataFromFifo_syncb & ~RegNext(io.ReadTxDataFromFifo_syncb, false.B)){
ReadTxDataFromFifo_tck := false.B
}
TxStartFrm & io.TxUsedData & Flop
TxData := io.txReq.bits
assert( ~(io.txReq.ready & ~io.txReq.valid) )
}

16
src/main/scala/Switch/mac/MacTilelink.scala
View File

@@ -32,12 +32,15 @@ abstract class MacTileLinkBase() extends Module{
val RxReady = Output(Bool())
val txReq = Decoupled(UInt(8.W))
val TxStartFrm_wb = Output(Bool())
val TxStartFrm_syncb = Input(Bool())
val TxEndFrm_wb = Output(Bool())
val TxData_wb = Output(UInt(8.W))
val ReadTxDataFromFifo_sync = Input(Bool())
// val TxData_wb = Output(UInt(8.W))
// val ReadTxDataFromFifo_sync = Input(Bool())
// Tx Status signals
val RetryCntLatched = Input(UInt(4.W)) // Latched Retry Counter
@@ -143,7 +146,7 @@ abstract class MacTileLinkBase() extends Module{
val txRetryPulse = io.TxRetrySync & ~RegNext(io.TxRetrySync, false.B)
val txDonePulse = io.TxDoneSync & ~RegNext(io.TxDoneSync, false.B)
val txAbortPulse = io.TxAbortSync & ~RegNext(io.TxAbortSync, false.B)
val ReadTxDataFromFifoSyncPluse = io.ReadTxDataFromFifo_sync & ~RegNext(io.ReadTxDataFromFifo_sync, false.B)
// val ReadTxDataFromFifoSyncPluse = io.ReadTxDataFromFifo_sync & ~RegNext(io.ReadTxDataFromFifo_sync, false.B)
io.PerPacketPad := RegEnable(io.txDeq.req.bits.PerPacketPad, false.B, io.txDeq.req.fire)
@@ -211,11 +214,12 @@ abstract class MacTileLinkBase() extends Module{
io.txDeq.data.ready := ReadTxDataFromFifoSyncPluse
// io.TxData_wb := io.txDeq.data.bits
io.txReq <> io.txDeq.data
// io.txDeq.data.ready := ReadTxDataFromFifoSyncPluse
assert( ~(io.txDeq.data.ready & ~io.txDeq.data.valid), "Assert Failed, Tx should never under run!" )
io.TxData_wb := io.txDeq.data.bits