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增加顶层的FPGA上的sync输出,修改测试用例

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This commit is contained in:
bacon
2025-08-11 18:04:35 +08:00
parent 24cbc2723c
commit 5448cfd23f
4 changed files with 106 additions and 19 deletions
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4
src/main/resources/FPGATop_MP.v
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@@ -36,6 +36,8 @@ module FPGATop(
output uDatOut_p,
output uDatOut_n,
output sync_out,
input sck,
input mosi,
output miso,
@@ -165,7 +167,7 @@ ShinTop i_ShinTop(
.io_iSync_1(),
.io_iSync_2(),
.io_iSync_3(),
.io_oSync_0(),
.io_oSync_0(sync_out),
.io_oSync_1(),
.io_oSync_2(),
.io_oSync_3(),

2
src/main/resources/constr.xdc
View File

@@ -16,7 +16,7 @@ set_property -dict {PACKAGE_PIN F13 IOSTANDARD TMDS_33} [get_ports uDatIn_p]
#CPU PC7
set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports interrupt]
set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports sync_out]
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports io_iqspi_sck]
set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports io_iqspi_data[0]]